Senior IC Package Design Engineer

SpaceX

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Irvine, CAAustin, TX
Salary
$165,000–$265,000 / yr
Posted
4 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $209k
This role $215k
$149k $277k
below market most similar roles pay here above market

This role pays more than 58% of similar roles. Most pay $177,250–$240,287 — the blue band above. At the midpoint, this role pays about $215k versus about $209k for comparable roles.

Based on 240 similar postings.

Employer

About SpaceX

SpaceX designs, manufactures, and launches advanced rockets and spacecraft with the mission of enabling humans to become a multi-planetary species. It operates the Falcon 9, Falcon Heavy, and Starship launch vehicles, as well as the Starlink satellite internet constellation.

SpaceX currently has 854 open roles on FindRole.

Listed pay typically runs $130,000–$165,000 across 591 roles with salary data.

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At a glance

TL;DR · Senior IC Package Design Engineer

The Sr. IC Package Design Engineer joins the Silicon Engineering team to develop next-generation ASICs for space and ground infrastructures. This role involves leading packaging for custom in-house ASICs and RFICs used in digital beam formers and modems. Key responsibilities include owning package selection, BGA configuration, and package structure while performing layout, optimization, design verification, and tapeout. The engineer must simulate and optimize signal and power integrity and RF performance while coordinating with cross-functional groups on silicon floor plans and pin outs. Required skills include experience with IC package design, substrate design for RF and high-speed die, and tools like Cadence APD+/SIP. Proficiency in SIWave, HFSS, and ADS for EM simulation is preferred to solve complex connectivity problems in previously unavailable locations.

What you'll do

  • Own and drive advanced package selection, BGA configuration, and package structure.
  • Execute package/SIP layout, optimization, design verification, and tapeout.
  • Coordinate with cross-functional groups on package selection, feasibility analysis, and design.
  • Optimize silicon floor plans, bump layouts, and package pin outs based on trade-offs.
  • Simulate and optimize signal integrity, power integrity, and RF performance of package designs.
  • Drive methodology, innovations, and productivity improvements in the package design process.

What we're looking for

  • Bachelor's degree in electrical engineering, computer engineering, or physics.
  • 5+ years of experience with IC package design.
  • Ability to work extended hours or weekends as needed to meet mission-critical deadlines.
  • Must be a U.S. citizen, national, lawful permanent resident, refugee, asylee, or eligible for Department of State authorization.
  • Experience with Co-packaged Optics (CPO) (preferred).
  • Thorough understanding of signal and power integrity fundamentals (preferred).
  • Substrate design experience for RF, digital, high-speed, and mixed-signal die (preferred).
  • Experience with Cadence APD+/SIP or similar design tools (preferred).

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