Package Design Methodology Engineer

Nvidia

Confirmed live yesterday High trust
Remote

Quick summary

Work type
Remote
Location
Santa Clara, CAAustin, TX
Salary
$136,000–$218,500 / yr
Posted
46 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $185k
This role $177k
$125k most similar roles pay here $236k

This role pays less than 54% of similar roles. Most pay $154,468–$216,062 — the shaded band above. At the midpoint, this role pays about $177k versus about $185k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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View all roles at Nvidia

At a glance

TL;DR · Package Design Methodology Engineer

As a Package Design Methodology Engineer on the Advanced Package Engineering team, you will develop production-grade EDA tooling and automation infrastructure for complex multi-die packages. You will design and implement VLSI tools for silicon and substrate design while creating applications that prioritize maintainability and ease of use for project engineers. Your daily work involves constructing, analyzing, and validating package designs across various production stages to optimize workflows for top designers. To succeed, you must possess strong programming fundamentals in Python and C++, including proficiency with data structures and object-oriented design. You will also apply AI/ML techniques to engineering workflows and utilize your knowledge of electrical engineering fundamentals, such as signal integrity and power delivery, to solve challenges involving chiplets, substrates, interposers, and heterogeneous interfaces for next-generation AI and HPC platform packages.

What you'll do

  • Design and implement VLSI tools for silicon and substrate design.
  • Develop applications to assist project engineers with a focus on maintainability and ease of use.
  • Create flows and methodologies to construct, analyze, and validate package designs throughout the production flow.
  • Optimize daily workflows for high-level package designers.
  • Build production-grade EDA tooling for multi-die packages and heterogeneous interfaces.
  • Integrate AI/ML techniques into engineering workflows and EDA environments.
  • Develop design flows for next-generation AI and HPC platform packages.

What we're looking for

  • BS in Computer Science, Electrical Engineering, or a related field (or equivalent experience).
  • 5+ years of experience developing flows and methodologies for package design used by engineering teams at scale.
  • Proficiency in Python and/or C++ with strong fundamentals in data structures, algorithms, and object-oriented design.
  • Demonstrated experience applying AI/ML techniques in engineering workflows or EDA environments.
  • Strong understanding of electrical engineering fundamentals relevant to VLSI package design, such as signal integrity or power delivery.
  • Expertise in developing package design flows and methodologies for interposer and IC physical design.

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