Package Design Methodology Engineer

Nvidia

Confirmed live today High trust

Remote

Quick summary

Work type: Remote
Location: Santa Clara, CAAustin, TX
Salary: $136,000–$218,500 / yr
Employment: Full-time
Posted: 5 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $208k

This role $177k

$121k $273k

below market most similar roles pay here above market

This role pays less than 72% of similar roles. Most pay $176,493–$240,287 — the blue band above. At the midpoint, this role pays about $177k versus about $208k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Package Design Methodology Engineer

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The Package Design Methodology Engineer joins the Advanced Package Engineering team to develop production-grade EDA tooling for complex multi-die packages. This role involves designing and implementing VLSI tools for silicon and substrate design, creating applications that prioritize maintainability and ease of use for project engineers. You will develop flows and methodologies to construct, analyze, and validate package designs across various production stages while optimizing daily workflows for package designers. Key requirements include proficiency in Python and C++, data structures, algorithms, and object-oriented design. Candidates must demonstrate experience applying AI/ML techniques to engineering workflows and possess a strong understanding of electrical engineering fundamentals like signal integrity and parasitic extraction. The work addresses the technical challenge of connecting dozens of chiplets across substrates and interposers for AI and HPC platforms.

Skills

Python C++ VLSI EDA AI ML LLMs Signal Integrity Power Delivery Parasitic Extraction IC Physical Design Data Structures Algorithms Object-Oriented Design Package Design HPC

What you'll do

Design and implement VLSI tools for silicon and substrate design.
Develop applications to enable project engineers with a focus on maintainability and ease of use.
Create flows and methodologies to construct, analyze, and validate package designs at various production stages.
Optimize daily workflows for the world's top package designers.
Develop production-grade EDA tooling for next-generation AI and HPC platform packages.
Apply AI/ML techniques to engineering workflows, including code generation and design analysis tools.

What we're looking for

BS in Computer Science, Electrical Engineering, or a related field, or equivalent experience.
5+ years of experience developing flows and methodologies for package design used by engineering teams at scale.
Proficiency in Python and/or C++, including data structures, algorithms, object-oriented design, and code quality practices.
Demonstrated experience applying AI/ML techniques in engineering workflows, such as LLMs for code generation or ML-assisted design analysis.
Strong understanding of electrical engineering fundamentals relevant to VLSI package design, including signal integrity and power delivery.
Good understanding of VLSI package design along with interposer and IC physical design (preferred).
Strong expertise in developing package design flows and methodologies (preferred).

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