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Physical Design Static Timing Analysis Logic Synthesis Floorplanning Clock-tree Synthesis Routing ECO RTL Python Tcl Perl Make AI Deep Learning LLMs EDA Tools +11 more Show less

Physical Design RTL to Tape-out Synthesis Timing Closure STA EM/IR Analysis Place and Route Clock Tree Synthesis Floorplanning Layout TCL Perl EDA Tools IC Design +9 more Show less

Physical Design RTL to Tape-out Synthesis Timing Closure STA EM/IR Analysis Place and Route Clock Tree Synthesis Floorplanning Layout TCL Perl EDA Tools +8 more Show less

ASIC Physical Design Synthesis STA P&R DFT CMOS UPF Low Power Design Floor Planning Timing Closure IR Drop Analysis Physical Verification ECO Mixed Signal AI Flow +11 more Show less

Physical Design EDA Tools Synopsys Fusion Compiler Cadence Innovus Flow Automation Silicon Design Automation +2 more Show less

STA PrimeTime Tempus ICC2 Innovus TCL Python Perl RTL GDS Spice Signal Integrity Layout Parasitic Extraction ASIC Back-end Design CTS POCV AOCV +12 more Show less

Verilog RTL Design Physical Design Synthesis Place and Route CPU Microarchitecture Logic Design Power Analysis Tapeout Flow +4 more Show less

ASIC Physical Design Static Timing Analysis Clock-Tree Synthesis ECO Synopsys ICC2 Fusion Compiler Cadence Innovus PrimeTime RedHawk Formality Conformal TCL Python Perl Pandas Machine Learning PPA Optimization +13 more Show less

Physical Design Synthesis Floorplanning Placement Routing Timing Closure STA DRC LVS Python TCL Shell Perl Synopsys Cadence ICC2 Fusion Compiler Innovus PrimeTime Tempus StarRC Calibre ICV +18 more Show less

Physical Design GPU SoC Synthesis Floorplanning Placement Routing Clock Tree Synthesis Timing Closure STA Signoff DRC LVS Python Tcl Shell Perl Synopsys Cadence ICC2 Fusion Compiler Innovus PrimeTime Tempus StarRC +20 more Show less

Physical Design Static Timing Analysis (STA) Power Analysis Logic Synthesis Equivalence Checking Placement Routing Cadence Synopsys Python Perl Tcl Make AI/ML LLM RTL GDSII +12 more Show less

CPU Design Micro-architecture Logic Design C C++ Python Perl Verilog VHDL Synthesis Design Verification Simulation Emulation Formal Verification Silicon Validation Computer Architecture Physical Design +12 more Show less

STA PrimeTime Tempus TCL Python Perl ICC2 Innovus RTL GDS Spice Signal Integrity Layout Parasitic Extraction Physical Design Timing Closure +10 more Show less

SPICE RTL Physical Design PLL Standard Cell Optimization Jitter Analysis Circuit Design Verification Hardware Engineering +4 more Show less

Synthesis Place and Route STA TCL Python Perl CSS HTML CGI Data Analytics CPU Design Automation +7 more Show less

ASIC SoC Physical Design RTL-to-GDSII Synthesis Place & Route STA Timing Closure Power Optimization TCL Python Synopsys Cadence PPA EM/IR Advanced Nodes +10 more Show less

ASIC RTL-to-GDSII Floorplanning Place and Route Static Timing Analysis PrimeTime TCL Python Cadence Innovus Cadence Genus Synopsys Formality Mentor Calibre Apache Redhawk Voltus Physical Verification +10 more Show less

Physical Design Static Timing Analysis Signal Integrity RTL Synthesis floor planning Clock Tree Synthesis Routing LVS DRC Antenna ERC Cadence Synopsys Mentor Atoptech GDS +12 more Show less