Physical Design Engineer

Amazon Inc

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Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $153,600–$215,000 / yr
Posted: 6 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $171k

This role $184k

$135k most similar roles pay here $224k

This role pays more than 72% of similar roles. Most pay $154,587–$187,250 — the shaded band above. At the midpoint, this role pays about $184k versus about $171k for comparable roles.

Based on 240 similar postings.

Employer

About Amazon Inc

Amazon Inc. is the world''s largest e-commerce and cloud computing company, operating the Amazon marketplace, AWS cloud platform, Prime subscription services, Alexa voice AI, and logistics infrastructure. Industry: E-Commerce & Cloud Computing

Amazon Inc currently has 560 open roles on FindRole.

Listed pay typically runs $143,700–$194,400 across 558 roles with salary data.

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At a glance

TL;DR · Physical Design Engineer

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The Physical Design Engineer joins the Amazon Leo team to develop digital chip SOCs for communication via Low Earth Orbit satellites and gateways. This role involves collaborating with RTL and logic designers to conduct architectural feasibility studies and explore power-performance-area tradeoffs for physical design closure. Day-to-day responsibilities include driving IO and core block implementation through synthesis, floor planning, bus and pin planning, place and route, power and clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, and ECO sign-off. The engineer will also develop physical design methodologies using AI flows and evaluate third-party IP. Key technical requirements include experience in ASIC implementation for deep sub-micron nodes, STA, DFT, and UPF flow for low power design. The work focuses on creating modems, high-speed interfaces, embedded processors, and DSP solutions in latest CMOS technologies.

What does a Physical Design Engineer earn?

Median $185425 from 36 postings across 9 companies.

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Skills

ASIC Physical Design Synthesis STA P&R DFT CMOS UPF Low Power Design Floor Planning Timing Closure IR Drop Analysis Physical Verification ECO Mixed Signal AI Flow

What you'll do

Conduct architectural feasibility studies and analyze power-performance-area tradeoffs for physical design closure.
Execute full physical implementation including synthesis, floor planning, and bus/pin planning.
Perform place and route, power/clock distribution, and congestion analysis.
Complete timing closure, IR drop analysis, and physical verification for SoC designs.
Develop new physical design methodologies while integrating AI-driven flows.
Evaluate third-party IP and provide technical recommendations for integration.
Integrate RF, analog, and mixed-signal blocks into digital top flows.
Implement low-power designs using UPF flow for advanced CMOS technologies.

What we're looking for

Must be a U.S. citizen, national, permanent resident, or granted asylum/refugee status for export control compliance.
Bachelor's degree in Electrical Engineering or a related field.
5+ years of experience in ASIC implementation including synthesis, STA, DFT, and P&R for deep sub-micron nodes.
Master's degree in Electrical or Communications Engineering or a related field (preferred).
7+ years of experience in ASIC implementation (preferred).
Experience using managed ML/AI solutions (preferred).
Experience integrating RF/Analog/Mixed signal blocks with digital top flows (preferred).
Strong exposure to UPF flow for low power design (preferred).