Physical Design Engineer

Broadcom

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Colorado Springs, COSan Jose, CA
Salary
$129,400–$207,000 / yr
Employment
Full-time
Posted
4 days ago
Freshness
Confirmed live today
Closes
Mar 27, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $209k
This role $168k
$113k most similar roles pay here $281k

This role pays less than 80% of similar roles. Most pay $176,531–$241,750 — the shaded band above. At the midpoint, this role pays about $168k versus about $209k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 172 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 125 roles with salary data.

Most-posted roles

View all roles at Broadcom

At a glance

TL;DR · Physical Design Engineer

The Physical Design Engineer joins the Data Center Solutions Group to support the development of PCIe Switch Products and Enterprise Storage Products for AI/ML ecosystems and mega datacenters. This role involves managing the full physical design cycle from RTL to silicon tape-out, including synthesis, physical verification, and timing closure through various strategies. The engineer will perform top-level STA, EM/IR analysis, floorplanning, layout, and clock tree synthesis using techniques like insertion reduction and skew balancing. They will also contribute to flow and methodology development while collaborating with IC Design RTL Engineers. Required technical skills include proficiency in TCL and PERL scripting along with experience in related EDA tools. The position requires a bachelor's degree in Electrical or Electronics Engineering and over twelve years of relevant experience in the physical design cycle.

What does a Physical Design Engineer earn?

Median $185425 from 36 postings across 9 companies.

See salary data

What you'll do

  • Execute the full physical design cycle from RTL to silicon tape-out.
  • Perform synthesis, physical verification, and timing closure using various methods and strategies.
  • Conduct top-level Static Timing Analysis (STA), EM/IR analysis, and floorplanning.
  • Implement Place and Route (P&R) and Clock Tree Synthesis (CTS).
  • Develop custom clock trees using insertion reduction and skew balancing techniques.
  • Develop flow methodologies for physical design processes.
  • Write TCL and PERL scripts to automate tasks in EDA tools.

What we're looking for

  • Bachelor's degree in Electrical Engineering or Electronics Engineering.
  • 12+ years of relevant experience.
  • Expertise in all Physical Design aspects from RTL to silicon tape-out.
  • Proficiency in TCL and PERL scripting for related EDA tools.
  • Experience with Synthesis, Physical Verification, and Timing Closure.
  • Excellent verbal and written communication skills.
  • In-depth experience in top-level STA EM/IR Analysis, Place and Route, and Clock Tree Synthesis (preferred).
  • In-depth experience in top-level floorplanning Flow and Methodology Development (preferred).

More like this

Similar roles

Physical Design Engineer

Broadcom

Colorado Springs, CO +1 4 days ago $121,900–$195,000
Physical Design RTL to Tape-out Synthesis Timing Closure STA EM/IR Analysis Place and Route Clock Tree Synthesis Floorplanning Layout TCL Perl EDA Tools IC Design
8+ yrs exp

Physical Design Engineer

Broadcom

San Jose, CA 39 days ago $143,800–$230,000
ASIC Physical Layout 3D IC DRC LVS TCL Python SI PI RDL Advanced Packaging PCB
10+ yrs exp

ASIC Implementation Engineer

Broadcom

San Jose, CA 3 days ago $143,800–$230,000
Physical Design STA Floorplanning Layout Clock Tree Synthesis EM/IR Analysis TCL Perl EDA Tools RTL Tape-out
8+ yrs exp

Physical IC Design Engineer

Broadcom

San Jose, CA 53 days ago
Physical Design RTL to Tape-out Synthesis Timing Closure EM/IR Analysis Place and Route Clock Tree Synthesis Floor-planning Layout TCL Perl EDA Tools ASIC PCIe Machine Learning
10+ yrs exp

Physical Design Engineer

Qualcomm

San Diego, CA 15 days ago $101,400–$152,200
ASIC RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Scripting Verification Validation
2+ yrs exp

Physical Design Engineer

Qualcomm

San Diego, CA 15 days ago $101,400–$152,200
ASIC RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Verification Scripting IC Package Logic Design