Physical Design and Timing Engineer Intern

What you'll do

• Drive physical design, power, and timing closure for high-frequency and low-power designs.
• Execute frontend and backend implementation tasks from RTL to GDSII.
• Run physical design experiments to improve design outcomes.
• Develop new flows and methodologies for physical design processes.
• Apply AI/ML techniques to accelerate design, analysis, and automation tasks.
• Perform Static Timing Analysis (STA) and power reduction analysis.
• Utilize industry-standard EDA tools for logic synthesis and equivalence checking.
• Write scripts in Perl, Tcl, Make, or Python to automate design tasks.

What we're looking for

• Pursuing an MS or Ph.D. in Electrical or Computer Engineering.
• Familiarity with applying AI/ML techniques to physical design workflows to accelerate design, analysis, or automation tasks.
• Knowledge of or experience with Static Timing Analysis (STA), power analysis, and power reduction.
• Some experience in logic synthesis and equivalence checking.
• Experience with physical optimization, such as placement, routing, and clock tree.
• Some background in industry-standard EDA tools like Cadence, Synopsys, or Siemens.
• Proficiency in programming and scripting languages such as Perl, Tcl, Make, and Python.
• Hands-on experience applying AI/ML models or LLM-based tools to solve EDA or physical design problems (preferred).