Physical Design and Timing Engineer Intern

Nvidia

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Employment
Intern
Posted
3 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

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How this pay compares to similar roles

Similar $161k
$103k most similar roles pay here $220k

This listing doesn't post a salary. Most similar roles pay $114,400–$208,000.

Based on 240 similar postings.

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 909 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 893 roles with salary data.

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At a glance

TL;DR · Physical Design and Timing Engineer Intern

Role Posting Log in to save

The Physical Design and Timing Engineer Intern - Summer 2027 joins a dynamic team to drive physical design, power, and timing closure for high-frequency and low-power designs. This role involves driving frontend and backend implementation from RTL to GDSII while running physical design experiments and developing new flows and methodologies. The candidate will work with industry-standard EDA tools from vendors like Cadence, Synopsys, or Siemens. Required skills include knowledge of Static Timing Analysis, power analysis, power reduction, logic synthesis, equivalence checking, and physical optimization tasks such as placement, routing, and clock tree design. Proficiency in scripting languages including Perl, Tcl, Make, and Python is required. Additionally, the role focuses on applying AI/ML techniques or LLM-based tools to accelerate design workflows, analysis, and automation tasks within the semiconductor hardware domain.

Skills

Physical Design Static Timing Analysis (STA) Power Analysis Logic Synthesis Equivalence Checking Placement Routing Cadence Synopsys Python Perl Tcl Make AI/ML LLM RTL GDSII

What you'll do

  • Drive physical design, power, and timing closure for high-frequency and low-power designs.
  • Execute frontend and backend implementation tasks from RTL to GDSII.
  • Conduct physical design experiments to improve performance and reliability.
  • Develop new flows and methodologies for the physical design process.
  • Apply AI/ML techniques to accelerate design analysis and automation tasks.
  • Perform static timing analysis (STA) and power reduction activities.
  • Execute logic synthesis and equivalence checking for integrated circuits.
  • Automate design workflows using scripting languages like Python, Tcl, Perl, or Make.

What we're looking for

  • Pursuing an MS or Ph.D. in Electrical or Computer Engineering.
  • Familiarity with applying AI/ML techniques to physical design workflows for acceleration and automation.
  • Knowledge of or experience with Static Timing Analysis (STA), power analysis, and power reduction.
  • Some experience in logic synthesis and equivalence checking.
  • Experience with physical optimization including placement, routing, and clock tree.
  • Background in industry-standard EDA tools such as Cadence, Synopsys, or Siemens.
  • Proficiency in programming and scripting languages like Perl, Tcl, Make, and Python.
  • Hands-on experience applying AI/ML models or LLM-based tools to solve EDA problems (preferred); previous work experience in physical design (preferred).

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