CPU Server Physical Design Methodology, Infrastructure and Automation Engineer

Qualcomm

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$142,200–$213,400 / yr
Posted
67 days ago
Freshness
Confirmed live yesterday
Closes
Jan 2, 2027

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $212k
This role $178k
$129k most similar roles pay here $264k

This role pays less than 65% of similar roles. Most pay $174,900–$248,400 — the shaded band above. At the midpoint, this role pays about $178k versus about $212k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 623 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 603 roles with salary data.

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At a glance

TL;DR · CPU Server Physical Design Methodology, Infrastructure and Automation Engineer

The CPU Server Physical Design Methodology, Infrastructure and Automation Engineer joins the CPU Engineering team to implement infrastructure improvements and automation for next-generation CPUs. Working with cross-functional teams including physical design, CAD, methodology, and STA, the engineer will bring up design infrastructure and dashboards across multiple domains. Day-to-day responsibilities involve collaborating with block level implementation teams to analyze and improve optimization methods while developing new prediction models and automation for rapid timing, power, and area estimation. The role requires proficiency in scripting languages such as TCL, Python, Perl, CSS, HTML, JS, and CGI. Candidates must possess experience in synthesis, place and route, and signoff timing and power analysis. Additionally, the role utilizes data analytics to identify design bottlenecks and uses AI-assisted utilities to provide visual aids for productivity enhancement and scalability.

What you'll do

  • Implement infrastructure improvements and automation for next-generation CPU designs.
  • Develop design infrastructure and dashboards for multiple CPU designs and domains.
  • Analyze and improve optimization methods for block-level implementation teams.
  • Create prediction models for rapid timing, power, and area estimation.
  • Use data analytics to identify and root cause design bottlenecks.
  • Develop scripts and tools to represent complex data metrics for productivity and scalability.
  • Utilize AI-assisted utilities and models to provide visual aids for design analysis.

What we're looking for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 2+ years of experience.
  • Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 1+ year of experience.
  • PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • Experience with synthesis, place and route, and signoff timing/power analysis.
  • Proficiency in scripting languages including TCL, Python, Perl, CSS, HTML, JS, and CGI.
  • Understanding of industry standard tools for synthesis, place & route, STA, and design signoff.
  • Data analytics skills to identify design bottlenecks and provide visual aids using AI-assisted utilities.
  • Software and programming skills to represent complex data metrics for productivity enhancement and scalability.

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