Senior Physical Design Engineer

Amd

Confirmed live today High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CA
Salary: $210,400–$315,600 / yr
Posted: 2 days ago
Freshness: Confirmed live today
Closes: Sep 22, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $182k

This role $263k

$123k most similar roles pay here $336k

This role pays more than 93% of similar roles. Most pay $154,377–$209,625 — the shaded band above. At the midpoint, this role pays about $263k versus about $182k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 394 open roles on FindRole.

Listed pay typically runs $164,000–$246,000 across 394 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · Senior Physical Design Engineer

Role Posting Log in to save

As a Senior Physical Design Engineer, you will join a team developing next-generation AI and high-performance computing silicon. You will lead and contribute to advanced-node physical design for complex ASIC and SoC products, focusing on implementation, timing closure, signoff, and PPA optimization across block, subsystem, and chip-level designs. Your daily work involves performing static timing analysis, clock-tree synthesis, and engineering change strategies while developing automated design flows and machine learning-driven optimization initiatives. You will utilize industry-standard tools including Synopsys ICC2, Fusion Compiler, PrimeTime, PrimeTime PX, PrimeShield, RedHawk, Formality, and Conformal. To succeed, you must possess scripting skills in TCL, Python, Perl, or Pandas to enhance design quality and predictability. This role addresses the technical challenges of delivering high-quality silicon on leading-edge process technologies for advanced computing applications.

Skills

ASIC Physical Design Static Timing Analysis Clock-Tree Synthesis ECO Synopsys ICC2 Fusion Compiler Cadence Innovus PrimeTime RedHawk Formality Conformal TCL Python Perl Pandas Machine Learning PPA Optimization

What you'll do

Lead physical design activities across block, subsystem, and chip-level implementations for complex ASIC and SoC products.
Drive timing closure, signoff readiness, and PPA optimization for advanced-node designs.
Develop and enhance physical design methodologies, design flows, and automation solutions.
Perform static timing analysis, variation-aware timing analysis, and clock-tree optimization.
Define and execute engineering change (ECO) strategies throughout the implementation and signoff phases.
Support formal verification, physical verification, and tapeout preparation activities.
Analyze design data and trends to improve design quality, predictability, and efficiency.
Contribute to AI-assisted and machine learning-driven design optimization initiatives.

What we're looking for

Lead physical design activities across block, subsystem, and chip-level implementations.
Drive timing closure, signoff readiness, and PPA optimization for advanced-node designs.
Develop and enhance physical design methodologies, design flows, and automation solutions.
Perform static timing analysis, variation-aware timing analysis, and clock-tree optimization.
Execute engineering change (ECO) strategies and support formal/physical verification and tapeout preparation.
Experience with ASIC physical design, implementation, and timing closure (preferred).
Experience with industry-standard tools like Synopsys ICC2, Fusion Compiler, or Cadence Innovus (preferred).
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field (preferred).

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