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UVM System Verilog Python CHI AMBA PCIe CXL Fabric Interconnects Generative AI Simulation +5 more Show less

PCIe UVM System Verilog Python CHI AXI Simulation Generative AI Coverage Signoff +4 more Show less

FPGA VHDL System Verilog UVM OSVVM Quartus Modelsim Questa Sim Python MATLAB Simulink JIRA GIT DSP RTL ASIC LabVIEW AXI Avalon NIOS +15 more Show less

VHDL UVM FPGA ASIC CPLD Intel Quartus Lattice Diamond Microsemi Libero Mentor Graphics Expedition PCIe AXI SERDES DMA MIL-STD-1553 DO-254 System on Chip High Speed Data Interfaces +12 more Show less

SystemVerilog UVM VCS GDB RISCV C Assertion-based Verification Functional Coverage Random Stimulus Firmware ASIC Verification Memory Subsystem High Speed IO Object Oriented Programming +9 more Show less

ASIC RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Verification Scripting Circuit Design Layout +5 more Show less

UVM OVM SystemVerilog Assertions (SVA) Verilog VHDL Python TCL Perl Mixed-Signal Verification Logic Synthesis Static Timing Analysis Formal Verification Place and Route EDA Tools CMOS Bipolar Scripting +12 more Show less

System Verilog UVM ASIC Verification Python Perl C C++ Emulation Formal Verification SoC Architecture Silicon Bring-up Post-Silicon Debug +7 more Show less

System Verilog UVM VCS C C++ Python Perl Shell ASIC Verification RTL FPGA Debussy GDB DDR LPDDR +10 more Show less

SystemVerilog UVM Python TCL Perl LLM Gate Level Simulation UPF PCIe USB DDR Formal Verification Emulation Simulators Waveform Viewers RTL +11 more Show less

DFT Verilog SystemVerilog ATPG Scan MBIST LBIST Boundary Scan UVM OVM RTL Design Static Timing Analysis Python Tcl Perl Shell Synopsys DFT Compiler TestMAX PrimeTime VCS Cadence tool s FPGA +17 more Show less

C C++ Ada RTOS Bare-metal AMD/Xilinx UltraScale+ MPSoC MIL-STD-1553 Robot Framework LDRA VectorCAST V-model DO-178 MIL-HDBK-516C JSSSEH +9 more Show less

Physical Verification DRC LVS ERC Antenna ESD SVRF Calibre Python TCL Perl PDK CAD AI Automation Silicon Design +11 more Show less

Go Distributed Systems CI/CD AWS Kubernetes GitHub Policy-as-Code Developer Infrastructure Observability AI-assisted Development source-control integration +6 more Show less

UVM System Verilog Python Formal Verification PCIe CXL AMBA CHI Fabric Interconnects Generative AI Simulation Coverage Signoff SVTB +8 more Show less

System Verilog UVM C C++ Python Perl EDA Tools Digital Design Computer Architecture ASIC High-speed Interface Protocols Simulation Regression Analysis Functional Coverage Constrained Random Verification +10 more Show less

SystemVerilog UVM C++ Python Perl EDA Tools RTL Simulation Logic Equivalence Checking DPI-C high-performance computing Co-simulation Hardware Emulation Linting Static Analysis Waveform Debugging Testbench Architecture +11 more Show less

SystemVerilog UVM C++ Python Perl EDA Tools RTL Simulation Logic Equivalence Checking DPI-C High-Performance Computing Co-simulation Hardware Emulation Linting Static Analysis Waveform Debugging Testbench Architecture +11 more Show less

SystemVerilog UVM C++ Python Perl EDA Tools RTL Simulation Logic Equivalence Checking DPI-C High-Performance Computing Co-simulation Hardware Emulation Linting Static Analysis Waveform Debugging Testbench Architecture +11 more Show less

SystemVerilog UVM C++ Python Perl EDA Tools RTL Simulation Logic Equivalence Checking DPI-C High-Performance Computing Co-simulation Hardware Emulation Linting Static Analysis Waveform Debugging Testbench Architecture +11 more Show less