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RTL Verilog SystemVerilog VHDL ASIC LPDDR HBM NoC CPU x86 ARM Cache Controller Memory Subsystem Digital Design Synthesis Timing Closure Physical Design Gate Level Simulation Power Analysis RTL Design Verification +15 more Show less

Python C# VLSI technologies mixed-signal semiconductor physics High-Speed test and characterization DDR 2/3/4/5 LPDDR 2/3/4/5 Oscilloscopes TDRs/VNAs J-BERT Board Design concepts ASIC device level characterization test automation development problem solving skills verbal communications skills written communications skills project management methodology updates +13 more Show less

HFSS ADS MATLAB Cadence PowerSI/DC Allegro Simbeor HSpice ICAT Seasim Power Integrity simulation tools 3-D field solvers VNA TDR Scopes Transmission line theory Channel modeling Signal integrity concepts Electromagnetic theory Coupling mechanisms High-speed DDR links NRZ and PAM4 SerDes PCB development PI analysis +18 more Show less