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ASIC Design RTL Coding Digital Design HBM LPDDR DDR NoC SRAM Cache Controller x86 ARM Gate Level Simulation Synthesis Timing Closure Power Analysis Hardware Architecture +11 more Show less

Go PostgreSQL Docker Kafka Lua Clickhouse SaltStack Prometheus Python Rust C++ SQL MySQL Unix Linux TCP/IP HTTP TLS DNS BGP +15 more Show less

Python C# Test Automation VLSI Mixed-Signal DDR LPDDR Signal Integrity Power Integrity Oscilloscopes J-BERT Schematic Review Layout +8 more Show less

UVM System Verilog Python Formal Verification PCIe CXL AMBA CHI JEDEC Memory Controller Generative AI Verification Methodology +7 more Show less

ASIC Design RTL Coding HBM LPDDR DDR NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis Digital Design Hardware Architecture +11 more Show less

DDR C C++ Python Linux Firmware Bootloaders Kernel Debugging Android QNX SoC Root Cause Analysis Performance Profiling Memory Management Scripting Validation Frameworks +11 more Show less

ASIC Design RTL Coding HBM LPDDR DDR NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis Digital Design Hardware Architecture +11 more Show less

Verilog SystemVerilog C SoC RTL Firmware Emulation Post-silicon Validation Silicon Bring-up DDR Cache Interconnect Computer Architecture Testbench Automation Debug Infrastructure +11 more Show less

DDR LPDDR PCDDR HBM PHY ASIC Signal Integrity Power Integrity Unix Perl TCL Mixed-Signal Design High-Speed Links +8 more Show less