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DDR Validation Lead, Staff

Qualcomm

San Diego, CA +1 11 days ago $145,600–$218,400
Actively hiring Confirmed live today Trusted Below market
LPDDR5X LPDDR6 DDR C C++ ASIC FPGA Post-Silicon Debug NoC Cache, coherency SI/PI Firmware Regression Infrastructure Automation Frameworks Memory Training Power Management
5+ yrs exp
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DDR Mixed-Signal Circuit Design Engineer

Apple Inc

Waltham, MA 24 days ago $165,800–$292,400
Actively hiring Confirmed live today Trusted Above market
Analog/Mixed-Signal Circuit Design PHY Design Verilog HDL EMIR SigEM SoC Architecture Delay Locked Loops Phase Interpolators Delay Lines Duty Cycle Correctors pre silicon verification Design Methodologies
10+ yrs exp
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Design Verification Engineer, DDR Memory Subsystem

Microsoft

27 days ago $102,100–$202,200
Actively hiring Confirmed live today Trusted Below market
UVM System Verilog Formal Verification Python PCIe CXL AMBA CHI JEDEC Memory Controller IP Verification Generative AI Simulation SVTB
2+ yrs exp Hybrid
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DDR Design Engineer

Apple Inc

Austin, TX 40 days ago
Actively hiring Confirmed live today Low trust
Verilog SystemVerilog RTL Design DDR PHY Logic Synthesis Timing Constraints DFT Equivalence Checking State Machines Clock Domain Crossing Assertions Static Checkers Silicon Bring-up Power Characterization
10+ yrs exp
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DDR Design Engineer

Apple Inc

San Diego, CA 40 days ago $175,000–$308,500
Actively hiring Confirmed live today Trusted Above market
Verilog SystemVerilog RTL Design DDR PHY Logic Synthesis Timing Constraints Unified Power Format Equivalence Checking Design For Test Scan Concept Clock Domain Crossing Assertions
10+ yrs exp
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DDR Design Engineer

Apple Inc

Beaverton, OR 40 days ago
Actively hiring Confirmed live today Low trust
Verilog SystemVerilog RTL Design DDR PHY Logic Synthesis Timing Constraints Unified Power Format DFT Equivalence Checking Assertion Writing Clock Domain Crossing State Machines Data Paths Static Checkers Silicon Bring-up
10+ yrs exp
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DDR Design Engineer

Apple Inc

Cupertino, CA 40 days ago $184,700–$324,800
Actively hiring Confirmed live today Trusted Above market
Verilog SystemVerilog RTL Design DDR PHY Logic Synthesis Timing Constraints Unified Power Format Equivalence Checking Design For Test Scan Concept Clock Domain Crossing Assertions
10+ yrs exp
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DDR Design Engineer

Apple Inc

Waltham, MA 40 days ago $165,800–$292,400
Actively hiring Confirmed live today Trusted Above market
Verilog SystemVerilog RTL Design DDR PHY Logic Synthesis Timing Constraints DFT Scan Concept Equivalence Checking Clock Domain Crossing State Machines Data Paths
10+ yrs exp
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DDR Design Engineer

Apple Inc

Irvine, CA 40 days ago $175,000–$308,500
Actively hiring Confirmed live today Trusted Above market
Verilog SystemVerilog RTL Design DDR PHY Logic Synthesis Timing Constraints DFT Scan Concept Equivalence Checking Clock Domain Crossing State Machines Data Paths Assertion Writing Silicon Bring-up Power Characterization
10+ yrs exp
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DDR Design Engineer

Apple Inc

Waltham, MA 40 days ago $116,400–$203,000
Actively hiring Confirmed live today Trusted Below market
Verilog SystemVerilog RTL Design DDR PHY Logic Synthesis Timing Constraints Unified Power Format Equivalence Checking DFT Scan Concept Clock Domain Crossing
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DDR Design Engineer

Apple Inc

San Diego, CA 40 days ago $122,700–$214,300
Actively hiring Confirmed live today Trusted Competitive pay
Verilog SystemVerilog RTL Design DDR PHY Logic Synthesis Timing Constraints DFT Scan Concept Equivalence Checking Clock Domain Crossing State Machines Data Paths Assertion Writing
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DDR Design Engineer

Apple Inc

Irvine, CA 40 days ago $122,700–$214,300
Actively hiring Confirmed live today Trusted Competitive pay
Verilog SystemVerilog RTL Design DDR PHY Logic Synthesis Timing Constraints DFT Scan Concept Equivalence Checking Clock Domain Crossing State Machines Data Paths
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DDR Design Engineer

Apple Inc

Beaverton, OR 40 days ago
Actively hiring Confirmed live yesterday Low trust
Verilog SystemVerilog RTL Design DDR PHY Logic Synthesis Timing Constraints Unified Power Format DFT Equivalence Checking Clock Domain Crossing State Machines Data Paths Assertion Writing Static Checkers Silicon Bring-up Power Characterization
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Next-Gen High-Speed HBM LPDDR Memory Subsystem ASIC Digital Design Engineer

Qualcomm

San Diego, CA 40 days ago $145,600–$218,400
Actively hiring Confirmed live today Trusted Competitive pay
ASIC Design RTL Coding Hardware Architecture LPDDR HBM NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Physical Design Gate Level Simulation Power Analysis Digital Design ISA Architecture
4+ yrs exp
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Next-Gen High-Speed HBM LPDDR Memory Controller ASIC Digital Design Engineer

Qualcomm

San Diego, CA 40 days ago $145,600–$218,400
Actively hiring Confirmed live today Trusted Competitive pay
ASIC Design RTL Coding Front-end Digital Design Hardware Architecture LPDDR HBM SRAM Cache Controller NoC x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis ISA Architecture
4+ yrs exp
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Senior Engineer, DDR Customer Engineering Software

Qualcomm

Santa Clara, CA 40 days ago $125,400–$188,200
Actively hiring Confirmed live today High trust Competitive pay
DDR Memory Architecture C C++ Python Embedded Linux Firmware Bootloaders Kernel Debugging Platform Bring-Up Cache Coherency Performance Profiling Root Cause Analysis Android QNX SoC Architecture Memory Management Stress Validation
2+ yrs exp
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DDRSS Validation Engineer

Qualcomm

San Diego, CA 40 days ago $145,600–$218,400
Actively hiring Confirmed live today Low trust Competitive pay
Verilog SystemVerilog C SoC Validation RTL Simulation Emulation Post-Silicon Validation Firmware Development ASIC Design Computer Architecture DDR Cache Interconnect Silicon Bring-up Automation
6+ yrs exp
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Senior Post-Silicon DDR Characterization Engineer

Arm Holdings

Chandler, AZ 46 days ago $161,500–$218,500
Actively hiring Confirmed live today High trust Competitive pay
DDR LPDDR Post-Silicon Validation C C++ Python Arm Assembly Linux Bare-Metal PHY Logic Analyzers Firmware Data Analysis
Hybrid
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Senior Software Engineer, Addressing Team

Cloudflare, Inc

Austin, TX +2 56 days ago
Actively hiring Confirmed live today High trust
Go PostgreSQL Docker Kafka Lua Clickhouse SaltStack Prometheus Python Rust C++ MySQL TCP/IP HTTP/S/TLS DNS Unix Linux Distributed Systems BGP Anycast
Hybrid
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