Quick summary
- Work type
- On-site
- Location
- —
- Salary
- $116,400–$203,000 / yr
- Posted
- 15 days ago
- Freshness
- Confirmed live today
Market check
Salary context
Below market
How this pay compares to similar roles
Similar $205k
This role $160k
$101k
most similar roles pay here
$257k
This role pays less than 80% of similar roles. Most pay $167,400–$241,750 — the shaded band above. At the midpoint, this role pays about $160k versus about $205k for comparable roles.
Based on 240 similar postings.
Employer
About Apple Inc
Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
Apple Inc currently has 3513 open roles on FindRole.
Listed pay typically runs $165,800–$277,600 across 2730 roles with salary data.
Most-posted roles
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At a glance
TL;DR · DDR Design Engineer
As a DDR Design Engineer, you will join the DDR PHY design team to develop high-performance, low-power designs. You will be involved in all phases of the logic design lifecycle, including concept study, architecture definition, design, verification, silicon bring-up, and characterization. Your daily responsibilities include performing concept studies regarding performance, gate count, and power; writing detailed design specifications and test plans; and providing high-quality RTL descriptions with assertions. You will utilize formal tools and static checkers to ensure RTL quality while driving functional coverage and timing closure. The role requires proficiency in Verilog or SystemVerilog, state machines, data paths, arbitration, clock domain crossing logic, and logic synthesis. Additional technical skills include Design For Test, scan concepts, Unified Power Format, and Equivalence checking within a mixed-signal environment for DDR PHY applications.
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DDR Design Engineer
Apple Inc
Cupertino, CA
161 days ago
$129,300–$225,300
Verilog
SystemVerilog
RTL Design
DDR PHY
Logic Synthesis
Timing Closure
Unified Power Format
DFT
Scan
Assertion Writing
State Machines
Clock Domain Crossing
Equivalence Checking
Mixed-Signal
Silicon Bring-up