Quick summary
- Work type
- On-site
- Location
- —
- Salary
- $122,700–$214,300 / yr
- Posted
- 15 days ago
- Freshness
- Confirmed live today
Market check
Salary context
Below market
How this pay compares to similar roles
Similar $204k
This role $168k
$108k
most similar roles pay here
$256k
This role pays less than 68% of similar roles. Most pay $167,175–$241,750 — the shaded band above. At the midpoint, this role pays about $168k versus about $204k for comparable roles.
Based on 240 similar postings.
Employer
About Apple Inc
Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
Apple Inc currently has 3513 open roles on FindRole.
Listed pay typically runs $165,800–$277,600 across 2730 roles with salary data.
Most-posted roles
- Software Engineer 287
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- Engineering Program Manager 64
- Design Verification Engineer 49
- SoC Physical Design Engineer 43
At a glance
TL;DR · DDR Design Engineer
As a DDR Design Engineer, you will join the DDR PHY design team to develop high-performance, low power designs. You will be involved in all phases of the design cycle, including concept study, architecture definition, design, verification, silicon bring-up, and characterization. Your daily responsibilities involve performing concept studies regarding performance, gate count, and power for digital designs while writing detailed specifications and test plans alongside architecture and circuit designers. You will provide high-quality RTL descriptions with assertions, utilizing formal tools and static checkers to ensure quality. Key tasks include driving functional and code coverage, achieving timing closure, and supporting silicon bring-up. Required skills include Verilog or SystemVerilog for RTL design, state machine development, data paths, arbitration, clock domain crossing logic, logic synthesis, timing constraints, Unified Power Format, and Equivalence checking in a mixed-signal environment.
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DDR Design Engineer
Apple Inc
San Diego, CA
15 days ago
$122,700–$214,300
Verilog
SystemVerilog
RTL Design
DDR PHY
Logic Synthesis
Timing Closure
Unified Power Format
DFT
Scan
Equivalence Checking
Assertion Writing
State Machines
Clock Domain Crossing
Mixed-Signal
Silicon Bring-up