Quick summary
- Work type
- On-site
- Location
- —
- Salary
- $165,800–$292,400 / yr
- Posted
- 15 days ago
- Freshness
- Confirmed live today
Market check
Salary context
Above market
How this pay compares to similar roles
Similar $204k
This role $229k
$129k
most similar roles pay here
$310k
This role pays more than 70% of similar roles. Most pay $167,175–$241,750 — the shaded band above. At the midpoint, this role pays about $229k versus about $204k for comparable roles.
Based on 240 similar postings.
Employer
About Apple Inc
Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
Apple Inc currently has 3513 open roles on FindRole.
Listed pay typically runs $165,800–$277,600 across 2730 roles with salary data.
Most-posted roles
- Software Engineer 287
- Machine Learning Engineer 126
- Engineering Program Manager 64
- Design Verification Engineer 49
- SoC Physical Design Engineer 43
At a glance
TL;DR · DDR Design Engineer
As a DDR Design Engineer, you will join the DDR PHY design team to develop high-performance, low-power designs. You will be involved in all phases of the design cycle, including concept study, architecture definition, design, verification, silicon bring-up, and characterization. Your daily responsibilities include performing concept studies regarding performance, gate count, and power; writing detailed design specifications and test plans; and providing high-quality RTL descriptions with assertions. You will utilize formal tools and static checkers to ensure quality while driving functional coverage and timing closure. The role requires expertise in Verilog or SystemVerilog, state machines, data paths, arbitration, clock domain crossing logic, and logic synthesis. Additional technical skills include Unified Power Format for simulation and electrical rule checking, as well as experience with Design For Test and scan concepts within a mixed-signal environment.
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DDR Design Engineer
Apple Inc
Irvine, CA
15 days ago
$175,000–$308,500
Verilog
SystemVerilog
RTL Design
DDR PHY
Logic Synthesis
Timing Closure
DFT
Unified Power Format
Equivalence Checking
Assertion Writing
State Machines
Clock Domain Crossing
Mixed-Signal
Static Checkers
10+ yrs exp