DDR Design Engineer

As a DDR Design Engineer within the DDR PHY design team, you will contribute to high-performance, low power applications by participating in all phases of the design cycle, from concept study and architecture definition to silicon bring-up and characterization. You will perform concept studies regarding performance, gate count, and power while drafting detailed design specifications and test plans alongside architects and verification engineers. Your daily work involves providing high-quality RTL descriptions including assertions, utilizing formal tools and static checkers for quality assurance, and driving functional coverage and timing closure. Key technical requirements include proficiency in Verilog or SystemVerilog, state machine design, data paths, arbitration, clock domain crossing logic, and Unified Power Format. You will also manage logic synthesis, timing constraints, and Design For Test considerations within a mixed-signal environment to ensure bug-free first silicon.