DDR Design Engineer

Apple Inc

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Quick summary

Work type
On-site
Location
Irvine, CA
Salary
$175,000–$308,500 / yr
Posted
15 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $204k
This role $242k
$128k most similar roles pay here $328k

This role pays more than 78% of similar roles. Most pay $167,175–$241,750 — the shaded band above. At the midpoint, this role pays about $242k versus about $204k for comparable roles.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3513 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2730 roles with salary data.

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At a glance

TL;DR · DDR Design Engineer

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As a DDR Design Engineer, you will join the DDR PHY design team to develop high-performance, low-power designs for upcoming products. You will be involved in all phases of the design cycle, including concept study, architecture definition, design, verification, silicon bring-up, and characterization. Your daily responsibilities include performing concept studies regarding performance, gate count, and power; writing detailed design specifications and test plans; and providing high-quality RTL descriptions with assertions. You will utilize formal tools and static checkers to ensure quality while driving functional coverage and timing closure. The role requires expertise in Verilog or SystemVerilog, state machines, data paths, arbitration, clock domain crossing logic, and logic synthesis. Additional technical skills include Design For Test, scan concepts, Unified Power Format for simulation and synthesis, and experience in mixed-signal environments.

Skills

Verilog SystemVerilog RTL Design DDR PHY Logic Synthesis Timing Closure DFT Unified Power Format Equivalence Checking Assertion Writing State Machines Clock Domain Crossing Mixed-Signal Static Checkers

What you'll do

  • Perform concept studies to provide direction on performance, gate count, and power for digital designs.
  • Write detailed design specifications and test plans in collaboration with architecture and verification teams.
  • Develop high-quality RTL descriptions including assertions using Verilog or SystemVerilog.
  • Utilize formal tools and static checkers to ensure high-quality RTL code.
  • Drive functional and code coverage as well as timing closure for assigned designs.
  • Support design verification to ensure bug-free first silicon.
  • Perform silicon bring-up, performance characterization, and power characterization.
  • Design state machines, data paths, arbitration, and clock domain crossing logic.

What we're looking for

  • BS degree in a technical discipline.
  • Minimum 10 years of relevant experience.
  • RTL design using Verilog or SystemVerilog and assertion writing (preferred).
  • Design of state machines, data paths, arbitration, and clock domain crossing logic (preferred).
  • Logic synthesis and timing constraints (preferred).
  • Exposure to Design For Test and writing DFT friendly RTL (preferred).
  • Unified Power Format for simulation, synthesis, and electrical rule checking (preferred).
  • Prior experience in DDR PHY design and mixed-signal environment (preferred).

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