DDRSS Validation Engineer

Qualcomm

Confirmed live today Low trust

Quick summary

Work type: On-site
Location: San Diego, CA
Salary: $145,600–$218,400 / yr
Posted: 40 days ago
Freshness: Confirmed live today
Closes: Mar 16, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $199k

This role $182k

$135k $245k

below market most similar roles pay here above market

This role pays less than 55% of similar roles. Most pay $168,500–$229,100 — the blue band above. At the midpoint, this role pays about $182k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · DDRSS Validation Engineer

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The DDRSS Validation Engineer (RTL + Silicon Debug) joins the ASICS Engineering group to support next-generation SoC platforms. This role involves driving end-to-end validation of SoC subsystems, including DDR, memory controllers, cache, and interconnects across RTL simulation, emulation, and post-silicon environments. The engineer will perform deep debug of functional issues, root-cause failures in testbenches, and analyze silicon timing and stability. Key responsibilities include developing and maintaining production-quality firmware in C to manage DDRSS IP sequences, frequency, and power management. The position requires proficiency in Verilog, SystemVerilog, and C for embedded systems. The work focuses on bridging the gap between design and system validation by developing debug infrastructure and automation to improve failure triage and turnaround time for complex memory systems.

Skills

Verilog SystemVerilog C SoC Validation RTL Simulation Emulation Post-Silicon Validation Firmware Development ASIC Design Computer Architecture DDR Cache Interconnect Silicon Bring-up Automation

What you'll do

Drive end-to-end validation of SoC subsystems including DDR, memory controllers, cache, and interconnects.
Perform deep debug of functional issues in RTL simulations, testbenches, and silicon environments.
Develop and maintain production-quality firmware in C for DDRSS IP sequences and power management.
Execute silicon bring-up and validate system-level use cases across simulation and emulation platforms.
Analyze silicon failures related to timing, stability, and performance.
Develop tools, debug infrastructure, and automation to improve validation efficiency and data collection.
Root-cause failures in firmware-driven flows and RTL simulations.

What we're looking for

Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC experience.
Master's degree in Science, Engineering, or related field and 3+ years of ASIC experience.
PhD in Science, Engineering, or related field and 2+ years of ASIC experience.
6–9 years of experience in SoC validation, design verification, or post-silicon validation.
Strong debug skills in Verilog/SystemVerilog simulation environments.
Experience with firmware development in C for embedded systems.
Hands-on experience with silicon bring-up, debug, and validation.
Solid understanding of computer architecture, SoC subsystems, and memory systems.

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