DDR Validation Lead, Staff

Qualcomm

Confirmed live today Trusted

Quick summary

Work type: On-site
Location: San Diego, CAAustin, TX
Salary: $145,600–$218,400 / yr
Posted: 11 days ago
Freshness: Confirmed live today
Closes: Apr 14, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $210k

This role $182k

$132k $272k

below market most similar roles pay here above market

This role pays less than 67% of similar roles. Most pay $177,250–$241,750 — the blue band above. At the midpoint, this role pays about $182k versus about $210k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 575 open roles on FindRole.

Listed pay typically runs $147,900–$221,900 across 550 roles with salary data.

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At a glance

TL;DR · DDR Validation Lead, Staff

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The DDR Validation Lead, Staff (AI Accelerator Platform) joins the System Validation & Emulation team to ensure end-to-end silicon quality for next-generation LPDDR5X and LPDDR6 memory subsystems. This role leads memory bring-up, performance validation, and system stress testing across pre-silicon and post-silicon phases for AI Accelerator and flagship mobile platforms. Key responsibilities include defining validation strategies, executing training validation, and leading debug for DDR controllers, PHYs, and firmware. The position requires characterizing bandwidth, latency, and QoS while validating interactions between the CPU, GPU, NPU, and NoC. Candidates must possess expertise in LPDDR4/5/5X/6 architectures, cache coherency, and power management. Technical proficiency in C/C++ and low-level software development is required to build scalable automation, regression infrastructure, and debug analytics frameworks for complex system-level issues.

Skills

LPDDR5X LPDDR6 DDR C C++ ASIC FPGA Post-Silicon Debug NoC Cache, coherency SI/PI Firmware Regression Infrastructure Automation Frameworks Memory Training Power Management

What you'll do

Define and execute DDR validation strategies across emulation, FPGA, and silicon platforms.
Drive LPDDR5X/LPDDR6 bring-up, training validation, frequency scaling, and low-power state validation.
Develop validation plans for memory functionality, performance, reliability, power, and corner-case scenarios.
Lead debug for DDR controller, PHY, firmware, SI/PI, timing, and system-level issues.
Validate interactions between DDR, CPU, GPU, NPU, cache hierarchy, NoC, and system software.
Characterize bandwidth, latency, QoS, memory pressure, and AI workloads.
Develop scalable automation, regression infrastructure, and debug analytics frameworks.
Partner with internal teams and DRAM vendors to root-cause and resolve hardware issues.

What we're looking for

BS in EE, CE, CS, or related field and 4+ years of ASIC design, verification, validation, or integration experience.
MS in EE, CE, CS, or related field and 3+ years of ASIC design, verification, validation, or integration experience.
PhD in EE, CE, CS, or related field and 2+ years of ASIC design, verification, validation, or integration experience.
5+ years of experience in DDR/memory subsystem validation or silicon bring-up.
Strong understanding of LPDDR4/5/5X/6 architectures, DDR controllers, PHYs, and memory training/calibration algorithms.
Proficiency in C/C++ and low-level software development.
Strong post-silicon debug experience.
Experience in mobile SoC, AI compute, automotive, or server platform validation (preferred).

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