Browse tech roles

Physical Design RTL-to-GDS SerDes PHY Logic Synthesis Place and Route Clock Tree Synthesis Physical Verification Static Timing Analysis Verilog Floorplanning IP Integration Logic Equivalence Checking Power Gating Scan Stitching EDA Tools Circuit Simulation Logic Simulation +12 more Show less

Verilog SystemVerilog Python TCL Perl VHDL Spice Power Analysis Formal Verification DRC LVS RC Extraction Machine Learning Data Analysis DFT Library Characterization EDA Tools +12 more Show less

Cadence Virtuoso Calibre ICV Thunder Python Perl Skill DRC LVS CMOS Mask Design Layout Design Signal Integrity Auto-routing APD package layout tool +11 more Show less

Mask Design Layout Design DRC LVS Python Perl Skill Calibre ICV Thunder Submicron CMOS Signal Integrity Auto-routing Netlists Silicon Interposers +10 more Show less

Power Integrity PDN Design di/dt Analysis Voltage Droop Sim-to-Si Correlation ASIC Circuit Design Bringup Characterization Voltage Regulator Decap Budgeting ML AI GPU CPU DAQ +11 more Show less

DFT SoC Architecture RTL Design Verilog UVM Post-Silicon Validation ATE Python Perl Tcl STA Place & Route Power Optimization Fuse Controller DFT IP Verification Synthesis +12 more Show less

Python C/C++ JavaScript Silicon Validation Computer Architecture Digital Design Circuit Analysis Signal Integrity Timing Analysis Fault Analysis Deep Learning Data Analysis Web Development BIOS Drivers Oscilloscope Logic Analyzer +12 more Show less

Physical Design EDA Tools PPA TCL Python C++ Perl Cadence Innovus Genus Tempus Quantus Joules STA UPF FSDB SAIF PyTorch NumPy SciPy scikit-learn ML AI Synthesis DFT +20 more Show less

Python C++ VLSI EDA AI ML LLMs Signal Integrity Power Delivery Parasitic Extraction IC Physical Design Data Structures Algorithms Object-Oriented Design Package Design HPC +11 more Show less

ASIC Design RTL Design Logic Synthesis Timing Analysis SoC Integration Python Perl C++ UCIe Digital Design Verification Methodology Boot Controllers Reset Controllers Memory Controllers DMA +10 more Show less

Circuit Design RTL Layout Spice EM/IR Analysis Static Timing Analysis PnR Logic Synthesis Python Perl Tcl Make Power Gating DRC LVS Post-Silicon Characterization Hardware Security AI/ML +13 more Show less

CPU Physical Design DTCO Synthesis Place-and-Route Static Timing Analysis PPA Python Tcl Perl timing-closure Silicon Design AI Tools Hardware Design Pathfinding +9 more Show less

Python C++ Machine Learning Agentic AI Large Language Models Combinatorial Optimization EDA VLSI Circuit Design CMOS Layout DRC LVS Spice Data Structures Algorithms Applied Math +11 more Show less

RTL Design Verilog Python Logic Synthesis DFT Physical Design Timing Closure Silicon Debug Power Optimization OCV Effects SOC Verification +6 more Show less

RTL Verilog ASIC Design Micro-architecture Logic Synthesis Timing Analysis C++ Python Perl VLSI Design Computer Architecture DMA Engines Bus Protocols Interconnect Networks Digital Systems Computer Arithmetic +11 more Show less

SOC Design RTL Design ASIC Design Physical Design DFT EDA Tools Python Perl Synthesis Padring SOC Integration Design Automation Front-end Chip Implementation +8 more Show less

ASIC Physical Design Logic Synthesis Static Timing Analysis (STA) Logic Equivalence Checking MTBF Analysis Timing Closure DFT Python Perl TCL Make EDA Tools ECO Generation +8 more Show less

Production Testing ASIC Microcontrollers Networking Servers PC Reference Validation Platforms Test Architecture Failure Diagnosis Test Plans System Test L10 L11 +7 more Show less

SRAM Design Cadence Virtuoso Transistor-level Circuit Design Layout Capture Logical Verification Silicon Testing SRAM Compiler Development SOC Design Codex Claude Code Debug +6 more Show less

GPU CPU SoC Tegra System Validation Oscilloscope Multimeter Logic Analyzer Electrical Engineering +4 more Show less