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CPU Design Micro-architecture Logic Design C C++ Python Perl Verilog VHDL Synthesis Design Verification Simulation Emulation Formal Verification Silicon Validation Computer Architecture Physical Design +12 more Show less

ASIC Circuit Design SPICE Python Perl CAD Automation SRAM Machine Learning Accelerators SOC Schematic Capture Layout +6 more Show less

PCB Design Cadence Allegro Mentor Graphics High-Speed Digital Design Signal Integrity Power Integrity EMI/RFI Control ODB++ CAD Layout Component Placement FCC UL European Regulations +8 more Show less

Verilog SystemVerilog C++ Python Perl Tcl SoC Design ASIC Design RTL Data Structures Algorithms Synopsys Fusion Compiler AI Coding Tools Claude Code Cursor +10 more Show less

DFT SoC Architecture RTL Design Verilog UVM Post-Silicon Validation ATE Python Perl Tcl STA Power Optimization Fuse Controller Verification Synthesis +10 more Show less

PCB Design Cadence Allegro Mentor Graphics Signal Integrity Power Integrity High-Speed Digital Design EMI/RFI Control ODB++ FCC UL European Regulations CAD Layout Component Placement Topology +9 more Show less

PCB Design PCB Layout System Validation Oscilloscopes Multimeters Logic Analyzers Linux Windows Tegra SoC GPU Bringup +6 more Show less

PCB Design Oscilloscopes Multimeters Logic Analyzers Linux Windows GPU Tegra System Design +4 more Show less

STA PrimeTime Tempus ICC2 Innovus TCL Python Perl RTL GDS Spice Signal Integrity Layout Parasitic Extraction ASIC Back-end Design CTS POCV AOCV +12 more Show less

RTL Verilog Python ASIC DFT Logic Synthesis PPA Silicon Debug Timing Closure Power Optimization Cross-talk OCV Scripting +8 more Show less

ASIC Design RTL Design SoC Integration Logic Synthesis Timing Analysis Python Perl C++ UCIe Digital Design Verification Methodology Memory Controllers DMA Boot Controllers Fuse Controllers +10 more Show less

SOC Integration RTL Design Python Perl EDA Tools Synthesis Padring Physical Design ASIC Design Design Automation Scripting DFT CAD +8 more Show less

ASIC Floorplan VLSI Computer Architecture Verilog System Verilog Python Perl C/C++ CAD Physical Design Timing Closure Clock Distribution Packaging +8 more Show less

Circuit Design Mixed-Signal Analog Digital Spice Static Timing Analysis EM/IR Analysis RTL Logic Synthesis Place and Route DFT Perl Tcl Make Automated Tools Transistor-level Analysis +11 more Show less

Python Data Pipelines LLM System Software Silicon Bring-up Productization Engineering DFT DFP ATE SLT BLT L10+ +7 more Show less

Silicon Bring-up Post-silicon Python Perl Linux Android JMP AI LLM Prompt Engineering Oscilloscopes Multimeters PPA Analysis Data Analysis Scripting Automation +11 more Show less

Verilog system Verilog UVM Python C++ C Perl Shell MySQL PHP Linux Unix Windows HDL Digital Systems Computer Organization Hardware Design Simulation Debugging Oscilloscopes +15 more Show less

Verilog system Verilog UVM Python C++ C Perl Shell MySQL PHP Linux Unix Windows HDL Logic Design Simulation Debugging Oscilloscopes Logic Analyzers +14 more Show less

SystemVerilog UVM assertion based verification C++ Python Formal Verification UPF DDR Cache SoC tape out post silicon debug PASIM Power Verification +9 more Show less

SoC Design RTL Verilog System Verilog UVM Python Perl Synthesis Physical Design Design Automation DFT CAD Scripting +8 more Show less