SRAM Design Engineer

Nvidia

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$116,000–$189,750 / yr
Employment
Full-time
Posted
12 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $198k
This role $153k
$101k $253k
below market most similar roles pay here above market

This role pays less than 82% of similar roles. Most pay $167,100–$229,100 — the blue band above. At the midpoint, this role pays about $153k versus about $198k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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View all roles at Nvidia

At a glance

TL;DR · SRAM Design Engineer

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The SRAM Design Engineer joins the Digital IP group to develop sophisticated SRAM compilers used extensively by internal SOC design partners. In this role, you will perform transistor-level circuit design, supervise layout implementation, and manage physical and logical verification for SRAM macros. You will also code efficient methods to automate the simultaneous assembly and validation of unique macros using compute resources. Key responsibilities include exploring future process nodes to optimize power, performance, and area characteristics while guiding silicon test and productization efforts. Required skills include a BSEE or equivalent, with an MSEE or PhD and two years of professional experience in SRAM design. You must be proficient with Cadence Virtuoso schematic and layout capture tools and demonstrate the ability to use AI coding and analysis tools like Codex and Claude Code.

Skills

SRAM Design Cadence Virtuoso Transistor-level Circuit Design Layout Capture Logical Verification Silicon Testing SRAM Compiler Development SOC Design Codex Claude Code Debug

What you'll do

  • Perform transistor-level circuit design for embedded SRAM macros.
  • Supervise layout implementation, physical and logical verification, and debug of SRAM macros.
  • Code automated systems for the simultaneous assembly and validation of multiple unique SRAM macros.
  • Explore future process nodes to develop techniques for optimal power, performance, and area.
  • Guide SOC design partners in achieving specific performance and cost goals.
  • Lead silicon test and characterization efforts for new hardware.
  • Prepare new silicon for real-world application requirements with productization teams.

What we're looking for

  • BSEE minimum (or equivalent experience).
  • MSEE or PhD with 2+ years of professional experience in SRAM design.
  • Familiarity with Cadence Virtuoso schematic and layout capture tools.
  • Willingness and ability to use AI effectively in day-to-day tasks.
  • Self-motivation, attention to detail, and good written, verbal, and presentation skills (preferred).
  • Skills in AI coding and analysis tools such as Codex and Claude Code (preferred).
  • Silicon testing and debugging experience (preferred).

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