below marketmost similar roles pay hereabove market
This role pays less than
53%
of similar roles. Most pay
$177,250–$229,100
— the blue band above.
At the midpoint, this role pays about
$204k
versus about
$203k
for comparable roles.
Based on 240 similar postings.
Employer
About Apple Inc
Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
Apple Inc currently has
3497 open roles
on FindRole.
Listed pay typically runs
$174,149–$277,600
across 2702 roles with salary data.
The Standard Cell Design Methodology & Flow Engineer joins the custom circuits team to support processor design in deep submicron technologies. This role involves developing standard cell library designs and establishing production flows by interfacing with internal CAD teams and foundries on PDK requirements. Key responsibilities include implementing digital blocks in Verilog or SystemVerilog, running simulations or formal checks for verification, and collaborating with technology teams on process requirements. The engineer will utilize data analysis and Machine Learning models to study circuit trends in timing, power, and area while detecting quality issues in large datasets. Required skills include proficiency in Python, TCL, or Perl, along with experience in Spice simulation, static timing analysis, library characterization, and various EDA tools for synthesis, place-route, and RC extraction.
Interface with internal CAD teams to plan production flows and coordinate foundry PDK requirements.
Work with technology teams to define new process requirements and enable relevant design tools.
Implement sophisticated digital blocks using Verilog or SystemVerilog.
Run simulations or formal checks to verify digital block designs.
Apply data analysis and Machine Learning models to study circuit trends in timing, power, and area.
Automate standard cell development and integration flows using Python, TCL, or Perl.
Perform library characterization including timing, power, and noise modeling.
Execute DRC/LVS, RC extraction, and synthesis flows for standard cell libraries.
What we're looking for
BS degree in a relevant field.
Minimum of 3 years of relevant industry experience.
At least 5+ years in Library Characterization, Timing/Power/CCS Noise/Variation Modeling, Liberty Formats, Spice simulation, Static Timing and Power Analysis flows, etc. (preferred)
Experience with timing modeling of large custom macros and complex sequential flops (preferred).
Exposure to Design For Test, scan concept and write DFT friendly RTL (preferred).
Understands all aspects of implementation specification, design, timing, power, and flow automation (preferred).
Data analysis and ML knowledge to study data trend and perform QA on big dataset with automation (preferred).
Flow automation skills in standard cells development and integration using Python/TCL/Perl (preferred).