Mask Design Engineer, Hardware

Nvidia

Confirmed live today High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CANVORAZWACA
Salary: $108,000–$184,000 / yr
Employment: Full-time
Posted: 4 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $187k

This role $146k

$95k $232k

below market most similar roles pay here above market

This role pays less than 88% of similar roles. Most pay $160,000–$214,000 — the blue band above. At the midpoint, this role pays about $146k versus about $187k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

Most-posted roles

View all roles at Nvidia

At a glance

TL;DR · Mask Design Engineer, Hardware

Role Posting Log in to save

The Senior Mask Design Engineer joins the hardware team to design and develop sophisticated, detailed layouts for silicon interposers used in NVIDIA products. Working closely with the Package Technical Lead and various design teams, the engineer performs physical layouts using Cadence tools, specifically Virtuoso. Key responsibilities include conducting design feasibility studies for size, cost, and system performance, studying layout floorplans, and performing custom layout and verification against netlists and design rules. The role requires expertise in submicron CMOS technologies, DRC and LVS checking flows, and debugging with verification tools like Calibre, ICV, and Thunder. Candidates should be proficient in scripting languages including Perl, Python, and Skill. This position solves complex packaging problems by proposing layout design trade-offs and resolving manufacturing and electrical design issues.

Skills

Cadence Virtuoso Calibre ICV Thunder Python Perl Skill DRC LVS CMOS Mask Design Layout Design Signal Integrity Auto-routing APD package layout tool

What you'll do

Perform physical layout for silicon interposers using Cadence tools.
Conduct design feasibility studies to evaluate package goals for size, cost, and performance.
Study layout floorplans and perform custom layout and verification against design rules and netlists.
Propose layout design trade-offs to the Package Technical Lead for resolution and implementation.
Resolve costs, manufacturing, and electrical design issues with various design teams.
Run and debug verification tools such as Calibre, ICV, and Thunder.
Customize DRC and LVS checking decks.
Develop scripts using Perl, Python, or Skill to support design workflows.

What we're looking for

Hold a B.S. in Electrical Engineering or equivalent experience.
Have 3+ years of proven experience in Mask and Layout Design.
Possess a deep understanding of layout concepts in submicron CMOS technologies.
Be an authority with Cadence layout tools, particularly Virtuoso.
Experience running and debugging with verification tools such as Calibre, ICV, and Thunder.
Be proficient in scripting languages like Perl, Python, and Skill.
Have knowledge of DRC and LVS checking flows and the ability to customize decks.
Knowledge of Integrity auto-routing is a plus (preferred).