Senior Mask Design Engineer, Hardware

Nvidia

Confirmed live today High trust

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CANVORAZWA
Salary: $136,000–$212,750 / yr
Employment: Full-time
Posted: 17 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $193k

This role $174k

$125k most similar roles pay here $236k

This role pays less than 71% of similar roles. Most pay $170,000–$216,250 — the shaded band above. At the midpoint, this role pays about $174k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1150 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 912 roles with salary data.

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At a glance

TL;DR · Senior Mask Design Engineer, Hardware

Role Posting Log in to save

As a Senior Mask Design Engineer – Hardware, you will join the hardware team to design and develop sophisticated, detailed layouts of silicon interposers for various products. Collaborating cross-functionally with package technical leads and signal integrity engineers, you will perform physical layouts using Cadence tools while conducting feasibility studies regarding size, cost, and system performance. Your daily responsibilities include studying layout floorplans, performing custom layouts, and verifying designs against netlists and rules. You must possess a deep understanding of submicron CMOS technologies and be an authority in Virtuoso. The role requires proficiency in scripting languages like Perl, Python, or Skill, along with experience using verification tools such as Calibre, ICV, and Thunder. You will also manage DRC and LVS checking flows to resolve manufacturing and electrical design issues within the packaging technology domain.

Skills

Cadence Virtuoso Calibre ICV Thunder Python Perl Skill DRC LVS Mask Design Layout Design Silicon Interposers Submicron CMOS Auto-routing APD Package Layout

What you'll do

Perform physical layout for silicon interposers using Cadence tools.
Conduct design feasibility studies to evaluate size, cost, and system performance goals.
Execute custom layout and verification against design rules and netlists.
Propose layout design trade-offs to the Package Technical Lead for resolution.
Resolve manufacturing, electrical design issues, and project scheduling constraints.
Run and debug designs using verification tools such as Calibre, ICV, and Thunder.
Develop and customize DRC and LVS checking flows.

What we're looking for

Hold a B.S. in Electrical Engineering or equivalent experience.
Minimum of 5+ years of proven experience in Mask and Layout Design.
Deep understanding of layout concepts in submicron CMOS technologies.
Authority with Cadence layout tools, particularly Virtuoso.
Proficiency in scripting languages such as Perl, Python, or Skill.
Knowledge of DRC and LVS checking flows and the ability to customize decks.
Experience running and debugging with verification tools like Calibre, ICV, or Thunder.
Knowledge of Integrity auto-routing (preferred); knowledge of APD package layout tool (preferred).

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