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UVM System Verilog Python CHI AMBA PCIe CXL Fabric Interconnects Generative AI Simulation +5 more Show less

PCIe UVM System Verilog Python CHI AXI Simulation Generative AI Coverage Signoff +4 more Show less

IC Packaging RF Design HFSS Momentum Signal Integrity Power Integrity FCBGA FCCSP WLCSP QFN Machine Learning Automation SERDES Thermal Simulation S-parameters Impedance Matching +11 more Show less

Swift Objective-C Python Java CI/CD Docker Kubernetes Git GitHub TeamCity Jenkins Generative AI Distributed Systems Test Automation Frameworks +9 more Show less

Swift Objective-C Python Java CI/CD Docker Kubernetes Git GitHub TeamCity Jenkins Generative AI SDET Test Automation Frameworks Distributed Systems Statistics-based Evaluation +11 more Show less

PCB Layout Allegro FPGA Verilog VHDL Python Lua C C++ USB 3.2 USB-PD Display Port PCIe I2C SPI DFT Data Analysis +12 more Show less

C C++ Objective-C Digital Signal Processing DSP Control Systems Test Automation Circuit Analysis Electromechanical Systems Root Cause Analysis NPI Modeling Simulations Algorithms +9 more Show less

FPGA VHDL System Verilog UVM OSVVM Quartus Modelsim Questa Sim Python MATLAB Simulink JIRA GIT DSP RTL ASIC LabVIEW AXI Avalon NIOS +15 more Show less

Electrical Engineering PCB Design Mentor Graphics xDX PSpice MATLAB LabVIEW Python Circuit Simulation Configuration Management Troubleshooting +5 more Show less

Mechanical Design Fan Rotor Design Technical Documentation Manufacturing Procurement Engineering Principles +1 more Show less

RFIC ASIC Design Cadence Virtuoso ADS LNA PLL 4G 5G 6G WLAN GPS Electro Magnetic simulation Neural Networks Physical Verification +10 more Show less

VHDL UVM FPGA ASIC CPLD Intel Quartus Lattice Diamond Microsemi Libero Mentor Graphics Expedition PCIe AXI SERDES DMA MIL-STD-1553 DO-254 System on Chip High Speed Data Interfaces +12 more Show less

Verilog VHDL SystemVerilog SOC Architecture DRAM Interface Design Synthesis Formal Verification Timing Closure Signal Integrity Physical Implementation HDL +6 more Show less

Physical Design Floorplanning Synthesis Placement Routing Clock Tree Synthesis Static Timing Analysis Physical Verification Formal Equivalence Power Optimization IR-drop Electromigration EDA Tools Low Power Verification +9 more Show less

Physical Design Place and Route Static Timing Analysis Physical Verification Formal Equivalency Verification IR-Drop Electromigration TCL Python Synopsys Fusion Compiler PrimeClosure Primetime Formality VCLP Star-RC Redhawk SC Cadence Innovus Siemens Calibre ASIC SOC +15 more Show less

Verilog SystemVerilog RTL Design SoC PCIe HBM AMBA AXI DMA Synthesis Timing Constraints CDC Lint RDC DFT Python Perl Agile Post-Silicon Debug +13 more Show less

ASIC RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Verification Scripting Circuit Design Layout +5 more Show less

RTL ASIC Design SerDes DDR PCIe USB UFS MIPI VCS Fusion Compiler PrimeTime Power Compiler Spyglass Python Perl DFT STA CDC GDSII +14 more Show less

Flip-chip BGA SerDes Signal Integrity Power Integrity Cadence APD Allegro Cadence SKILL ASIC HBM DDR5 RF/Microwave Automation High-Performance Computing 5G +9 more Show less

UVM OVM SystemVerilog Assertions (SVA) Verilog VHDL Python TCL Perl Mixed-Signal Verification Logic Synthesis Static Timing Analysis Formal Verification Place and Route EDA Tools CMOS Bipolar Scripting +12 more Show less