Senior Power Integrity Co-Design Engineer

Nvidia

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CA
Salary
$136,000–$218,500 / yr
Employment
Full-time
Posted
11 days ago
Freshness
Confirmed live yesterday

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $191k
This role $177k
$125k most similar roles pay here $236k

This role pays less than 55% of similar roles. Most pay $165,000–$216,250 — the shaded band above. At the midpoint, this role pays about $177k versus about $191k for comparable roles.

Based on 240 similar postings.

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1371 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1096 roles with salary data.

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At a glance

TL;DR · Senior Power Integrity Co-Design Engineer

The Senior Power Integrity Co-Design Engineer joins the SCG Architecture team to architect and deliver di/dt mitigation across silicon, package, board, and platform levels. This role serves as the connective tissue between architecture, silicon, and platform teams, translating product noise targets into shipped specifications while feeding findings back into future designs. Responsibilities include managing co-design trade-offs regarding voltage-noise, developing Sim-to-Si correlation methodologies, prototyping next-generation features like transient sense and droop response, and leading show-stopper noise bugs during bringup. The candidate must possess expertise in di/dt analysis, voltage droop, PDN design, decap budgeting, and voltage regulator response. Required skills include hands-on experience with scopes, probes, and DAQ systems for characterization. The role addresses the technical challenge of balancing V/F, power, noise, reliability, and thermal constraints within a multi-rail, multi-domain PDN at the SoC level.

What you'll do

  • Architect voltage-noise mitigation across the full stack including silicon, package, board, and platform levels.
  • Define product-level voltage noise targets and drive them to closure for final shipment sign-off.
  • Develop and own the Sim-to-Si correlation methodology to identify discrepancies between models and physical silicon.
  • Prototype and codify next-generation noise features such as transient sense and droop response.
  • Resolve critical show-stopper noise bugs during the hardware bringup phase.
  • Manage architecture-level trade-offs between voltage, frequency, power, reliability, and thermal constraints.
  • Translate product noise targets into technical specifications for cross-functional engineering teams.

What we're looking for

  • BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field (or equivalent experience).
  • 5+ years of experience in silicon power integrity, voltage noise, or PDN.
  • Deep expertise in at least one area: di/dt analysis and mitigation, voltage droop, PDN design, transient noise, decap budgeting, or voltage regulator response.
  • Experience with hands-on silicon bringup, characterization, and Sim-to-Si correlation using scopes, probes, and DAQ systems.
  • Ability to drive architecture-level co-design tradeoffs across power, reliability, and thermal constraints in a matrixed environment.
  • Proven ability to document technical specifications and lead noise bug resolution during product bringup.
  • Patents or publications in power integrity, voltage noise, PDN, or di/dt mitigation (preferred).
  • Experience with GPU, CPU, AI accelerator silicon, or applying ML/AI to noise modeling and feature optimization (preferred).

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