Power Integrity Engineer
Apple Inc
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How this pay compares to similar roles
This role pays less than 55% of similar roles. Most pay $165,000–$216,250 — the shaded band above. At the midpoint, this role pays about $177k versus about $191k for comparable roles.
Based on 240 similar postings.
Employer
Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing
Nvidia currently has 1371 open roles on FindRole.
Listed pay typically runs $184,000–$287,500 across 1096 roles with salary data.
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At a glance
The Senior Power Integrity Co-Design Engineer joins the SCG Architecture team to architect and deliver di/dt mitigation across silicon, package, board, and platform levels. This role serves as the connective tissue between architecture, silicon, and platform teams, translating product noise targets into shipped specifications while feeding findings back into future designs. Responsibilities include managing co-design trade-offs regarding voltage-noise, developing Sim-to-Si correlation methodologies, prototyping next-generation features like transient sense and droop response, and leading show-stopper noise bugs during bringup. The candidate must possess expertise in di/dt analysis, voltage droop, PDN design, decap budgeting, and voltage regulator response. Required skills include hands-on experience with scopes, probes, and DAQ systems for characterization. The role addresses the technical challenge of balancing V/F, power, noise, reliability, and thermal constraints within a multi-rail, multi-domain PDN at the SoC level.
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