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Python PCIe SerDes Ethernet DDR5 USB_3_x SGMII BERT oscilloscopes logic_analyzers VNAs protocol_analyzers multimeters high_speed_interfaces signal_integrity power_integrity waveform_analysis eye_diagrams jitter_analysis BER_measurements thermal_testing lab_automation schematics_and_layout_files networking_fundamentals packet_based_systems +20 more Show less

TCL PERL RUBY PYTHON C++ TetraMax Fastscan +2 more Show less

SystemVerilog UVM ASIC Emulation Formal verification Networking Python CI/CD Git JIRA Confluence Linux Docker Kubernetes +9 more Show less

UVM C++ SystemVerilog ASIC verification UCIe HBM controller Memory DFT DDR Custom HBM CI/CD +5 more Show less

SystemVerilog UVM Python Perl C++ ASIC Verification Emulation FormalVerification Docker CI/CD +6 more Show less

SystemVerilog UVM Python Perl Emulation FormalVerification SiliconBring-up Post-siliconDebug Scripting DataCenterTechnologies AINetworking ASICVerificationMethodologies +7 more Show less

Verilog System Verilog Python Perl TCL shell PCIe Ethernet MAC DDR LPDDR DMA engines AXI CHI APB AHB RDMA NVMe-over-TCP ASIC design flows simulation synthesis static timing analysis emulation formal verification +18 more Show less

Verilog SystemVerilog RTL Timing_Closure Power_Optimization Clock_Gating ASIC_Development_Flows Simulation Synthesis Static_Timing_Analysis Python Perl TCL Shell Emulation Prototyping Formal_Verification_Pods +12 more Show less

SystemVerilog UVM Perl Python Veloce Palladium Zebu HAPS IEV VC Formal PCIe CXL Ethernet RDMA DDR TCP +11 more Show less

ASIC FPGA RTL Synthesis Functional Verification Physical Layout Emulation Program Management Milestone Planning Risk Management Dependency Tracking Delivery Execution Silicon Engineering Hardware Systems Software Development Operations Management Cross-Functional Collaboration Technical Leadership Product Management CI/CD +15 more Show less

Synopsys_PrimeTime Cadence_Tempus TCL Python Perl SDC STA RTL DFT ASIC ARM_CPUSubsystem Third-party_IP_Integration Clocking_Architectures CDC_Analysis SpyGlass_CDC TCM CCD +12 more Show less

Verilog SystemVerilog Python Perl TCL shell programming CDC Spyglass digital design principles microarchitecture concepts buffering scheduling architectures +7 more Show less

Jtag Scan BIST ATPG TestMax Tetramax Tessent PrimeTime VCS Verilog System Verilog Gate level simulation DFT EDA tools Test Static Timing Analysis CI/CD +11 more Show less

Verilog SystemVerilog Python Perl Makefile AMBA AXI APB UPF SDC SVA ASIC CAD tools Simulation Synthesis STA LINT LEC CDC RDC Power estimation +14 more Show less

SystemVerilog UVM Python Perl C++ Data_center_technologies Hyperscalers AI_Networking Industry_standards Advanced_emulation Formal_verification_tools Silicon_debugging +7 more Show less

X-ray CSAM TDR FIB SEM TEM IR EMMI OBIRCH SIL LSM ATE Scan/ATPG MBIST JEDEC Python MATLAB LabVIEW SolidWorks AutoCAD Excel PowerPoint +17 more Show less

Keysight ADS Ansys HFSS Cadence APD SPICE Python Raptor-X MATLAB Vector Network Analysis IBIS 56G PAM4 SerDes HBM UCIe CoWoS EMIB 2.5D ASIC packaging +11 more Show less

SystemVerilog UVM Linux C C++ Python Perl Veloce Palladium Zebu HAPS Networking Dashboard_management CI/CD +9 more Show less

SystemVerilog UVM Linux C++ Python Perl Veloce Palladium Zebu HAPS CI/CD Networking Dashboard_management Emulation_platforms +9 more Show less

ASIC STA Hyperscale hierarchical analysis parasitic stitching IO budgeting flat parasitic extraction timing constraints timing closure ECO on-chip variation AOCV POCV voltage temperature aging-based timing derates Synopsys DC/DCG/FC Formality Cadence LEC Star-RCXT Quantus Synopsys Primetime PTPX Tweaker PrimeClosure Tempus TCL Perl Python +24 more Show less