Browse tech roles

System Verilog UVM ASIC Verification Python Perl C C++ Emulation Formal Verification SoC Architecture Silicon Bring-up Post-Silicon Debug +7 more Show less

Verilog System Verilog DFT ATPG RTL Design UVM OVM Python Tcl Perl Shell Synopsys DC Compiler PrimeTime Cadence Virtuoso VCS Static Timing Analysis FPGA HBM PCIe SerDes +15 more Show less

ASIC System Verilog UVM Veloce Palladium Zebu HAPS C C++ Python Perl Linux Networking Post-silicon Lab Bring-up Verification Methodology Silicon One +11 more Show less

ASIC FPGA RTL Verilog SystemVerilog VHDL EDA Tools Physical Design Timing Closure Power Optimization DFT Silicon Validation Device Drivers Low-level Software AI/ML Accelerators +10 more Show less

ASIC ATE 93000 Smartscale Exascale C C++ Java Python JMP AI ML Statistical Analysis DFT VLSI Silicon Debug Failure Analysis Data Analytics +12 more Show less

ATE Advantest 93000 Smartest 7 C C++ Java Perl Python DFT Scan ATPG JTAG MBIST PVT SerDes VLSI SOC +12 more Show less

DFT Python Perl Tcl Shell Scripting Verilog SystemVerilog LSF SDC EDA Tools ASIC Design Scan Insertion ATPG SPF Generation Pattern Simulation Regression Frameworks +11 more Show less

SystemVerilog UVM Verilog VHDL C++ Python Perl TCL Ethernet ASIC Verification Logic Design Electronic Circuit Design Object Oriented Programming Scripting +9 more Show less

ASIC Package Design PCB Design Python Perl SQL PowerBI Data Analytics Data Visualization Semiconductor Theory Transmission Lines Design Verification +7 more Show less

ASIC Package Design PCB Design Python Perl SQL PowerBI Data Analytics Data Visualization Semiconductor Theory Design Verification +6 more Show less

DFT ATPG Scan Insertion MBIST TAP LBIST Verilog Tessent SSN Mentor TestKompress TetraMax Fastscan IEEE1149.1 IEEE1149.6 IEE1687 IJTAG ICL PDL STA SerDes DDR PCIe +16 more Show less

Python Claude Innovus ICC2 Calibre Tcl Docker OpenAI API Pinecone Weaviate RAG LLM MLPD STA DRC EDA Tools Vector Databases +12 more Show less

Verilog System Verilog ASIC Design RTL Timing Closure Clock Gating post silicon validation Scripting Micro-architecture +4 more Show less

STA Verilog SystemVerilog ASIC Design Physical Design Spice ECO Timing Analysis Extraction PnR +5 more Show less

System Verilog UVM ASIC SoC Python Perl PCIe CXL Ethernet AHB AXI DDR Formal Verification Veloce HAPS Simulation Emulation +12 more Show less

SystemVerilog UVM Verilog Python Perl C C++ Linux ASIC Design Formal Verification Jasper Gold Veloce Palladium Zebu HAPS PCIe Ethernet RDMA TCP Fiber Channel P4 +16 more Show less

Physical Design STA DFT EDA Tools TCL Verilog RTL Logic Synthesis Low Power Design SERDES DRC Scan Memory BIST Chip Architecture Packaging Tape-out +11 more Show less

Verilog System Verilog ASIC Design RTL Python Perl TCL Micro-architecture Tape-out post silicon validation Simulation +6 more Show less

Signal Integrity Power Integrity ASIC PAM4 SerDes Cadence Sigrity Ansys HFSS Keysight ADS Cadence APD SPICE HBM UCIe CoWoS EMIB Vector Network Analysis IBIS Transmission Line Theory +12 more Show less

Signal Integrity Power Integrity ASIC Cadence Sigrity Ansys HFSS Keysight ADS Cadence APD SPICE PAM4 SerDes HBM UCIe CoWoS EMIB Vector Network Analysis IBIS +11 more Show less