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Solidworks Ansys Icepack Ansys Mechanical Python Excel Allegro Thermal Management PCB Design Simulations Profilometry Keyence ATE Test Hardware Mechanical Prototyping +8 more Show less

ASIC Implementation Design-for-Test ATPG Tessent TestMax Tetramax Verilog Gate Level Simulation VCS SDF Scan Insertion JTAG Tcl Python Perl Static Timing Analysis Post-Silicon Validation +12 more Show less

STA DFT RTL Design CDC RDC SDC Python TCL Perl Makefile Tessent PCIE BIST Scan Shift/Capture Conformal Verification +10 more Show less

ASIC Design Verification System Verilog UVM Python Perl Gate Level Simulation Emulation Formal Verification PCIe CXL Ethernet RDMA DDR TCP P4 Veloce Palladium Zebu HAPS OOP +15 more Show less

ASIC Signal Integrity Power Integrity Cadence Sigrity Ansys HFSS Keysight ADS Cadence APD SPICE PAM4 SerDes 2.5D Fanout HBM UCIe IBIS Vector Network Analysis Transmission Line Theory Electromagnetics +11 more Show less

Verilog System Verilog DFT MBIST AMBA AXI APB AHB JTAG UPF Formal Verification Linting CDC Checkers Synthesis Post-Silicon Debug Power Optimization Power Estimation +12 more Show less

IC Package Design Flip-chip BGA ASIC SerDes Signal Integrity Power Integrity HBM DDR5 Cadence APD Allegro Package Designer Cadence SKILL Physical Design Layout RF Microwave ADC DAC +12 more Show less

System Verilog UVM Python Perl ASIC Gate Level Simulation Veloce Palladium Zebu HAPS P4 PCIe CXL Ethernet RDMA DDR TCP Formal Verification +13 more Show less

System Verilog UVM Python Perl ASIC Design Verification Gate Level Simulation Veloce Palladium Zebu HAPS VC Formal IEV P4 PCIe CXL Ethernet RDMA DDR TCP +14 more Show less

System Verilog UVM Python TCL Perl Verdi DVE JTAG MBIST DFT Scan Architecture Boundary Scan ATE post silicon validation +9 more Show less

ASIC Implementation Synthesis Design for Test Floorplanning Place and Route Clock Methodology Power Planning Timing Closure Signal Integrity Physical Design Checks +5 more Show less

DFT MBIST ATE Verilog Python TCL Perl DVE Verdi SRAM DRAM Synopsys DesignWare SMS TestMax Mentor Graphics Tessent +10 more Show less

ASIC Design RTL Design Ethernet PCIe Python Perl Simulation Verification Synthesis Timing Closure Silicon Validation Architecture Definition high speed communication front end design +9 more Show less

DFT Verilog System Verilog ATPG JTAG Scan BIST VCS TestMax Tetramax Tessent PrimeTime Gate Level Simulation Post-Silicon Validation ATE P1687 Static Timing Analysis RTL EDA Tools +14 more Show less

Semiconductor Failure Analysis Root Cause Analysis Cross Section X-ray CSAM TDR FIB SEM TEM IR/EMMI/OBIRCH Solid Immersion Lens Laser Scanning Microscopy ATE Scan/ATPG MBIST LVP LVI/SMI LADA TIVA JEDEC IC Qualification +15 more Show less

ASIC Signal Integrity Power Integrity Cadence Sigrity Ansys HFSS Keysight ADS SPICE Cadence APD Ansys EM PAM4 SerDes IBIS Vector Network Analysis HBM UCIe CoWoS EMIB Transmission Line Theory Electromagnetics +14 more Show less

RTL-to-GDSII Physical Design Static Timing Analysis STA Innovus Tempus Primetime Redhawk Voltus Calibre Python TCL Perl Clock Tree Synthesis CTS Power Integrity Floorplanning Place and Route Equivalence Checks +14 more Show less

Cadence Allegro Python Perl TCL Verilog JMP Reliasoft Minitab FMEA Signal Integrity Power Design SerDes PCIe Gen5/6 800G Ethernet HTOL Burn-In HAST TC HTS ESD LU SER JEDEC AEC Telcordia CoWoS SoIC EMIB FPGA Schematic Generation Board Bring-up Failure Analysis +27 more Show less

ASIC Silicon Development Firmware Hardware Systems RTL Synthesis Functional Verification Physical Layout FPGA Emulation Post-Silicon Validation Micro-architecture Program Management Milestone Planning Risk Management +10 more Show less

ATE ASIC DFT Scan ATPG JTAG MBIST PVT SerDes C C++ Java Python Perl SOC VLSI 93k test methods Advantest 93000 Smartest 7 +14 more Show less