Staff Engineer, ASIC Design Verification

Samsung Semiconductor

Quick summary

Work type: On-site
Location: San Jose, CA · Folsom, CA
Salary: $163,000–$253,000 / yr
Posted: today

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Competitive pay

How this pay compares to similar roles

Similar $197k

This role $208k

$149k most similar roles pay here $264k

This role pays more than 64% of similar roles. Most pay $170,000–$223,700 — the shaded band above. At the midpoint, this role pays about $208k versus about $197k for comparable roles.

Based on 240 similar postings.

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About Samsung Semiconductor

Samsung Semiconductor is the global semiconductor business unit of Samsung Electronics, designing and manufacturing memory chips, logic semiconductors, and foundry solutions for a broad range of applications.

Samsung Semiconductor currently has 54 open roles on FindRole.

Listed pay typically runs $163,000–$253,000 across 54 roles with salary data.

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At a glance

TL;DR · Staff Engineer, ASIC Design Verification

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As a Staff Engineer in ASIC Design Verification at Samsung’s DRAM Development Lab, you will join a team dedicated to developing cutting-edge memory and storage solutions for cloud and data center applications. Your primary responsibilities include defining verification strategies, contributing to micro-architecture specifications, and architecting test benches using UVM. You’ll work closely with architects and design engineers to ensure comprehensive functional coverage while supporting post-silicon bring-up and debugging. Ideal candidates have a BE (MS preferred) in Computer/Electrical Engineering or Computer Science, along with 10+ years of experience in ASIC verification, expertise in C++, SystemVerilog, and UVM, and familiarity with emerging technologies like DDR, Custom HBM, and AI accelerators.

Skills

UVM C++ SystemVerilog ASIC verification UCIe HBM controller Memory DFT DDR Custom HBM CI/CD

What you'll do

Define and contribute to verification strategy and methodology.
Verify modules/subsystems of AI accelerators thoroughly.
Architect test benches and implement UVM components for testing.
Execute verification plans to achieve functional and code coverage targets.
Collaborate with architects and design engineers to define verification requirements.

What we're looking for

10+ years of experience in ASIC verification
Expertise in UVM and SystemVerilog for logic and SoC verification
Strong C++ skills for test bench creation and implementation
Experience with DDR, Custom HBM, and related IP level/SOC level verification
Understanding of emerging technologies like CXL, AI LLM accelerators
Daily onsite presence required at San Jose HQ or Folsom location

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