ASIC Design Engineer Technical Lead

Cisco

Remote

Quick summary

Work type: Remote
Location: San Jose, CA
Salary: $183,800–$263,600 / yr
Posted: 3 days ago
Closes: Aug 1, 2026

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $192k

This role $224k

$139k most similar roles pay here $277k

This role pays more than 82% of similar roles. Most pay $167,737–$216,250 — the shaded band above. At the midpoint, this role pays about $224k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 174 open roles on FindRole.

Listed pay typically runs $165,000–$241,400 across 174 roles with salary data.

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At a glance

TL;DR · ASIC Design Engineer Technical Lead

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Join Cisco’s Silicon One team as an experienced ASIC Design Engineer to contribute to the development of a unified silicon architecture for web-scale and service provider networks. In this role, you will participate in chip architecture definition, author design specifications, implement Verilog RTL, mentor junior engineers, collaborate with verification teams to address bugs, work closely with physical design teams to resolve timing issues, and perform diagnostic tests post-silicon validation. The ideal candidate has extensive experience in ASIC design, proficiency in Verilog/SystemVerilog, interactive debug tools, and resolving timing violations. Additional skills include digital design principles, microarchitecture concepts, CDC checks, Spyglass static analysis, and scripting languages like Python or Perl. This role offers a unique blend of startup culture within a large organization, providing ample opportunities for growth and mentorship in the fast-paced world of silicon architecture development.

Skills

Verilog SystemVerilog Python Perl TCL shell programming CDC Spyglass digital design principles microarchitecture concepts buffering scheduling architectures

What you'll do

Participate in chip architecture definition and contribute to discussions.
Author design specifications and review micro-architecture documents.
Implement Verilog RTL code to meet performance requirements.
Mentor junior engineers on project tasks and problem-solving techniques.
Collaborate with verification team to resolve design bugs and improve coverage.
Work with physical design team to address timing and place-and-route issues.
Triage, debug, and root cause simulation failures and customer issues.

What we're looking for

Bachelor’s degree in Electrical or Computer engineering with 10+ years of ASIC Design experience or Master’s degree and 8+ years.
Proficient in Verilog/System Verilog programming and interactive waveform debug.
Experience resolving timing violations through RTL modification and developing micro-architecture solutions.
Knowledge of digital design principles, buffering, scheduling architectures, CDC, and Spyglass static analysis.
Scripting skills with Python, Perl, TCL, or shell programming.

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