ASIC Engineering Technical Leader- STA

Cisco

Remote

Quick summary

Work type: Remote
Location: San Jose, CA
Salary: $210,600–$305,100 / yr
Posted: 19 days ago
Closes: Jul 24, 2026

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $200k

This role $258k

$147k most similar roles pay here $322k

This role pays more than 95% of similar roles. Most pay $177,250–$223,700 — the shaded band above. At the midpoint, this role pays about $258k versus about $200k for comparable roles.

Based on 239 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 174 open roles on FindRole.

Listed pay typically runs $165,000–$241,400 across 174 roles with salary data.

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At a glance

TL;DR · ASIC Engineering Technical Leader- STA

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Join Cisco's Silicon One Team as a senior ASIC design engineer, contributing to the development of cutting-edge silicon architecture for advanced process nodes. You will define and verify high-performance ASIC subsystems, oversee code creation and methodology, and drive innovative verification strategies across multi-disciplined engineering teams. Day-to-day responsibilities include managing complex IC designs, directing mixed-signal teams, and interfacing with vendors on technical issues. The role requires expertise in Synopsys tools for synthesis, formal verification, parasitic extraction, and static timing analysis, along with scripting languages like TCL and Perl. Ideal candidates have extensive experience in STA methodologies, hierarchical analysis, and timing closure techniques at advanced process nodes, ensuring robust design flows for high-volume product releases.

Skills

ASIC STA Hyperscale hierarchical analysis parasitic stitching IO budgeting flat parasitic extraction timing constraints timing closure ECO on-chip variation AOCV POCV voltage temperature aging-based timing derates Synopsys DC/DCG/FC Formality Cadence LEC Star-RCXT Quantus Synopsys Primetime Tempus TCL Perl Python

What you'll do

Oversees the definition and design of high-performance ASICs.
Creates guidelines and standards for complex development processes.
Develops innovative verification strategies for system-level testing.
Directs mixed-signal teams to define requirements and ensure specifications are met.
Interfaces with vendors and design leads on complex technical issues.
Drives technology design rules to develop innovative chip packages.

What we're looking for

10+ years of experience in ASIC design and development.
Experience with STA including hierarchical analysis and parasitic stitching.
Expertise in timing closure and ECO for advanced process nodes.
Knowledge of on-chip variation techniques such as AOCV, POCV, and derates.
Bachelor’s degree or higher in a relevant field (Electrical Engineering, Computer Science).
Proficiency with Synopsys DC/DCG/FC synthesis tools.
Experience using Static Timing Analysis tools like Synopsys Primetime/Cadence Tempus.

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