ASIC Design Verification Engineer

Cisco

Remote

Quick summary

Work type
Remote
Location
San Jose, CA
Salary
$152,500–$219,200 / yr
Posted
8 days ago
Closes
Aug 25, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $191k
This role $186k
$138k most similar roles pay here $238k

This role pays less than 53% of similar roles. Most pay $165,250–$216,250 — the shaded band above. At the midpoint, this role pays about $186k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 179 open roles on FindRole.

Listed pay typically runs $165,000–$241,400 across 179 roles with salary data.

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View all roles at Cisco

At a glance

TL;DR · ASIC Design Verification Engineer

As an ASIC Design Verification Engineer at Cisco, you will join a dynamic team within the data center solutions division, where you’ll contribute to the development of cutting-edge chips and systems. Your daily tasks will include architecting DV infrastructure, creating comprehensive test plans, and executing simulations to ensure robust verification and coverage for complex chip designs. You will collaborate closely with designers, architects, and software teams to integrate hardware and software seamlessly, optimizing performance for Cisco’s high-end switching products. The role requires expertise in System Verilog and UVM, as well as experience in ASIC design and verification processes, emulation, formal verification, and AI agents. This position offers a unique blend of startup culture with the resources of a leading networking company, focusing on large-scale data center solutions.

What you'll do

  • Architect and develop DV infrastructure for complex chips.
  • Create comprehensive test plans and execute them rigorously.
  • Ensure robust verification and coverage for design blocks and top-level integration.
  • Construct simulation models and performance analysis tools.
  • Collaborate with hardware and software teams to integrate solutions seamlessly.

What we're looking for

  • Bachelor's degree in a relevant field and 5+ years of experience or Master's with 3+ years.
  • Expertise in System Verilog and Universal Verification Methodology (UVM).
  • Experience in ASIC design verification processes, debugging methodologies, and tools.
  • Prior work on verifying blocks/clusters or full chip level for ASICs.
  • Knowledge of emulation techniques and formal verification methods.
  • Background in networking and experience with AI agents for verification.

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