ASIC Design Engineering Technical Leader

Cisco

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$183,800–$263,600 / yr
Posted
2 days ago
Closes
Jul 10, 2026

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $193k
This role $224k
$144k most similar roles pay here $276k

This role pays more than 81% of similar roles. Most pay $169,875–$216,250 — the shaded band above. At the midpoint, this role pays about $224k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 174 open roles on FindRole.

Listed pay typically runs $165,000–$241,400 across 174 roles with salary data.

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At a glance

TL;DR · ASIC Design Engineering Technical Leader

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Join the high-performance ASIC team at Cisco as a senior architect responsible for driving the architecture and micro-architecture of critical subsystems in next-generation data center silicon. You will design and implement high-frequency, high-performance RTL in Verilog/SystemVerilog, lead technical reviews, and collaborate with verification and physical design teams to ensure robust silicon delivery. Mentor engineers and conduct root-cause analysis across various validation stages. The role requires expertise in high-performance RTL design, timing closure, power optimization, and familiarity with ARM-based SoC architectures and protocols like AXI and CHI. Preferred candidates have experience with data center networking, storage architectures, and integrating third-party IP into complex SoC environments.

Skills

Verilog SystemVerilog RTL Timing_Closure Power_Optimization Clock_Gating ASIC_Development_Flows Simulation Synthesis Static_Timing_Analysis Python Perl TCL Shell Emulation Prototyping Formal_Verification_Pods

What you'll do

  • Drive the architecture and micro-architecture of high-performance ASIC subsystems.
  • Design and implement high-frequency, high-performance RTL in Verilog / System Verilog.
  • Lead design specifications and technical reviews for complex SoC subsystems.
  • Mentor engineers to elevate engineering rigor and design quality across teams.
  • Debug and root-cause analyze issues across simulation, system bring-up, and post-silicon validation.

What we're looking for

  • Bachelor’s degree in Electrical or Computer Engineering with 8+ years of ASIC experience.
  • Experience in high-performance RTL design using Verilog/SystemVerilog.
  • Expertise in timing closure, power optimization, and clock gating techniques.
  • Proficiency in ASIC development flows including simulation, synthesis, and static timing analysis.
  • Strong debug skills and ability to collaborate across multiple engineering teams.

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