ASIC Engineering Technical Leader - Emulation

Cisco

Hybrid

Quick summary

Work type
Hybrid
Location
San Jose, CA
Salary
$168,800–$241,200 / yr
Posted
2 days ago
Closes
Jul 10, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $199k
This role $205k
$150k most similar roles pay here $251k

This role pays more than 60% of similar roles. Most pay $173,512–$223,700 — the shaded band above. At the midpoint, this role pays about $205k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 174 open roles on FindRole.

Listed pay typically runs $165,000–$241,400 across 174 roles with salary data.

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At a glance

TL;DR · ASIC Engineering Technical Leader - Emulation

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As a senior verification architect at Cisco, you will set the vision and strategy for ASIC verification methodologies across multiple product lines, serving as a technical authority and mentor to foster innovation within verification teams. You will lead the architecture and implementation of scalable verification infrastructure, drive cross-functional initiatives to enhance efficiency and quality, and influence ASIC design to ensure robust verification processes. This role requires expertise in System Verilog, UVM, and scripting languages like Python or Perl, with a preference for experience in data center technologies and large-scale SoC architectures. You will also provide leadership in resolving complex issues during silicon validation, contributing to the advancement of industry standards and best practices.

Skills

SystemVerilog UVM Python Perl Emulation FormalVerification SiliconBring-up Post-siliconDebug Scripting DataCenterTechnologies AINetworking ASICVerificationMethodologies

What you'll do

  • Set vision and strategy for ASIC verification methodology across multiple programs.
  • Lead the architecture of scalable, reusable verification infrastructure and methodologies.
  • Drive cross-functional initiatives to enhance verification efficiency and quality at scale.
  • Influence ASIC architecture to enable robust verification and high-quality silicon production.
  • Provide technical leadership in resolving complex issues during bring-up and post-silicon validation.

What we're looking for

  • Extensive experience in ASIC verification methodologies and System Verilog.
  • Proven track record of leading verification teams or projects.
  • Expertise in UVM and scripting languages (Python, Perl).
  • Experience architecting scalable verification strategies for complex programs.
  • Deep knowledge of emulation and formal verification tools.

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