ASIC Design Verification Emulation Engineer

Cisco

Hybrid

Quick summary

Work type: Hybrid
Location: San Jose, CA
Salary: $165,000–$241,400 / yr
Posted: 2 days ago
Closes: Jul 10, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $191k

This role $203k

$136k most similar roles pay here $253k

This role pays more than 65% of similar roles. Most pay $165,250–$216,250 — the shaded band above. At the midpoint, this role pays about $203k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 174 open roles on FindRole.

Listed pay typically runs $165,000–$241,400 across 174 roles with salary data.

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At a glance

TL;DR · ASIC Design Verification Emulation Engineer

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As a Senior Verification Architect at Cisco, you will lead the strategic direction and execution of ASIC verification methodologies across various product lines, serving as a technical authority for verification teams and driving innovation in scalable infrastructure development. Your daily responsibilities include mentoring team members, enhancing verification efficiency through cross-functional initiatives, and influencing ASIC design to ensure robust verification processes. You will leverage System Verilog, UVM, and scripting languages like Python and C/C++ to architect complex verification strategies, while also staying abreast of industry trends and contributing to best practices in the field. This role is particularly relevant for those with experience in data center technologies or AI networking, offering opportunities to work on large-scale SoC architectures and advanced emulation tools at scale.

Skills

SystemVerilog UVM Python Perl C++ ASIC Verification Emulation FormalVerification Docker CI/CD

What you'll do

Set vision and strategy for ASIC verification methodology across multiple programs.
Lead the architecture and implementation of scalable verification infrastructure.
Drive cross-functional initiatives to enhance verification efficiency and quality.
Influence ASIC architecture to enable robust verification processes.
Serve as a subject matter expert on industry trends and new technologies.
Provide technical leadership in resolving complex issues during validation phases.

What we're looking for

Extensive experience in System Verilog and UVM for ASIC verification.
Proven track record of architecting verification strategies for complex ASIC programs.
Leadership in managing verification teams or projects.
Proficiency in scripting languages (Python, Perl) and C/C++ programming.
Expertise in data center, Hyperscaler, or AI Networking technologies preferred.
Experience with advanced emulation tools and formal verification at scale.

Careers

Qualcomm

San Diego, CA 17 days ago

SystemVerilog UVM SystemVerilog-UVM C++ C Perl Python VHDL Verilog AMBA_Bus_Protocol Formal_Verification Assertion_Based_Formal_Verification

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