ASIC Design Verification Engineer

Cisco

Hybrid

Quick summary

Work type: Hybrid
Location: San Jose, CA
Salary: $165,000–$241,400 / yr
Posted: 4 days ago
Closes: Jul 10, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $191k

This role $203k

$136k most similar roles pay here $253k

This role pays more than 65% of similar roles. Most pay $165,250–$216,250 — the shaded band above. At the midpoint, this role pays about $203k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 174 open roles on FindRole.

Listed pay typically runs $165,000–$241,400 across 174 roles with salary data.

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At a glance

TL;DR · ASIC Design Verification Engineer

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As a senior verification architect at Cisco, you will set the strategic direction for ASIC verification methodologies and execution across various programs and product lines, serving as a technical authority and mentor to foster innovation within verification teams. Your daily responsibilities include leading the architecture and implementation of scalable verification infrastructure, driving initiatives to enhance efficiency and quality, and influencing ASIC design to ensure robust verification processes. You will also provide expert guidance on industry trends and best practices while resolving complex issues during bring-up and post-silicon validation phases. The ideal candidate has extensive experience in System Verilog, UVM, scripting languages like Python or Perl, and C/C++ programming, with a preference for expertise in data center technologies, large-scale SoC architectures, and advanced verification tools at scale.

Skills

SystemVerilog UVM Python Perl C++ Data_center_technologies Hyperscalers AI_Networking Industry_standards Advanced_emulation Formal_verification_tools Silicon_debugging

What you'll do

Set vision and strategy for ASIC verification methodology across multiple programs.
Lead the architecture of scalable, reusable verification infrastructure and methodologies.
Drive initiatives to improve verification efficiency, quality, and coverage at scale.
Influence ASIC architecture to enable robust verification and high-quality silicon.
Provide technical leadership in resolving complex issues during bring-up and post-silicon validation.
Serve as a subject matter expert on industry trends and new technologies in verification.

What we're looking for

Extensive experience in System Verilog and UVM for ASIC verification.
Proven track record of architecting verification strategies for complex ASIC programs.
Leadership in managing verification teams or projects.
Proficiency in scripting languages (Python, Perl) and C/C++ programming.
Expertise in data center, Hyperscaler, or AI Networking technologies preferred.
Experience with advanced emulation, prototyping, and formal verification tools.