ASIC DFT Engineer

Broadcom

Quick summary

Work type: On-site
Location: San Jose, CAFort Collins, CO
Salary: $121,900–$195,000 / yr
Posted: 3 days ago
Closes: Aug 19, 2026
Nearby: 46 roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $191k

This role $158k

$109k most similar roles pay here $246k

This role pays less than 81% of similar roles. Most pay $165,250–$216,250 — the shaded band above. At the midpoint, this role pays about $158k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 97 open roles on FindRole.

Listed pay typically runs $120,000–$192,000 across 96 roles with salary data.

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At a glance

TL;DR · ASIC DFT Engineer

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Broadcom's ASIC Product Division in Fort Collins, Colorado, is hiring a senior DFT engineer to join their dynamic team. This role involves working on various phases of SoC DFT activities including architecture, test insertion and verification, pattern generation, coverage improvement, post-silicon debug, and yield enhancement to meet product test metrics. The candidate will focus on ATPG & Verification at the chip level, rapid bring-up at ATE, and RMA support while innovating new DFT solutions for 3nm and beyond technologies. Proficiency in TCL, PERL, RUBY, PYTHON, C++, and familiarity with tools like TetraMax and Fastscan are essential. The position requires a Bachelors or Masters degree in Electrical/Electronic/Computer Engineering along with extensive industry experience.

Skills

TCL PERL RUBY PYTHON C++ TetraMax Fastscan

What you'll do

Develop ATPG & verification at chip level for SoC designs.
Rapidly bring up ATE (Automatic Test Equipment) for new products.
Provide RMA support to address post-silicon test issues.
Innovate DFT solutions to tackle testability challenges in advanced nodes.
Improve coverage and yield through pattern generation and analysis.

What we're looking for

Bachelor's degree in EE/CE plus 8+ years or Master’s degree in EE/CE plus 6+ years of relevant industry experience.
Proficiency in scripting languages such as TCL, PERL, RUBY, PYTHON, and C++.
Expertise in ATPG & verification at chip level for SoC DFT activities.
Experience with rapid bring-up at ATE and RMA support.
Ability to innovate new DFT solutions for advanced node testability issues.

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