ASIC Design Verification Engineer

Cisco

Remote

Quick summary

Work type
Remote
Location
San Jose, CA
Salary
$152,500–$219,200 / yr
Posted
2 days ago
Closes
Jul 10, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $191k
This role $186k
$138k most similar roles pay here $234k

This role pays more than 50% of similar roles. Most pay $165,150–$216,250 — the shaded band above. At the midpoint, this role pays about $186k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 174 open roles on FindRole.

Listed pay typically runs $165,000–$241,400 across 174 roles with salary data.

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View all roles at Cisco

At a glance

TL;DR · ASIC Design Verification Engineer

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As an ASIC Design Verification Engineer at Cisco, you will join a dynamic team focused on advancing data center solutions by architecting and developing robust DV infrastructure for complex chips. Your daily tasks include building DV environments from scratch, creating comprehensive test plans using constraint-random and directed stimulus, ensuring thorough verification coverage through code and functional implementation, and collaborating with designers and software teams to debug issues during post-silicon bring-up. You will also support design testing in emulation environments, requiring expertise in System Verilog and UVM methodology, along with hands-on experience building scalable test benches using Perl or Python scripts. Ideal candidates have additional knowledge of formal verification tools and protocols such as PCIe, CXL, Ethernet, RDMA, DDR, or TCP, enhancing their ability to contribute effectively to Cisco’s cutting-edge hardware platforms.

Skills

SystemVerilog UVM Perl Python Veloce Palladium Zebu HAPS IEV VC Formal PCIe CXL Ethernet RDMA DDR TCP

What you'll do

  • Architect and develop DV infrastructure for block, cluster, and top-level verification.
  • Create comprehensive test plans using constraint-random and directed stimulus methods.
  • Implement and review code and functional coverage to ensure thorough verification.
  • Qualify RTL design by conducting Gate Level Simulations on netlists.
  • Debug issues during post-silicon bring-up and integration with cross-functional teams.

What we're looking for

  • Bachelor’s degree + 5 years or Master’s degree + 3 years of ASIC experience.
  • Proficient in System Verilog and UVM methodology.
  • Hands-on experience building reusable and scalable test benches.
  • Scripting skills with Perl and/or Python.
  • Experience in constraint-random and directed stimulus testing.
  • Collaboration with designers, architects, and software teams for debugging.

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