ASIC Engineering Technical Leader- DFT

Cisco

Remote

Quick summary

Work type: Remote
Location: San Jose, CA
Salary: $210,600–$305,100 / yr
Posted: 3 days ago
Closes: Aug 7, 2026

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $192k

This role $258k

$134k most similar roles pay here $323k

This role pays more than 97% of similar roles. Most pay $168,500–$216,250 — the shaded band above. At the midpoint, this role pays about $258k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 174 open roles on FindRole.

Listed pay typically runs $165,000–$241,400 across 174 roles with salary data.

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At a glance

TL;DR · ASIC Engineering Technical Leader- DFT

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As an ASIC Technical Lead in the Silicon One development organization at Cisco in San Jose, you will focus on Design-for-Test (DFT), defining and implementing post-silicon strategies to support automated test equipment (ATE) and in-system testing needs. You will develop innovative DFT IP and collaborate with multi-functional teams to integrate these features into RTL designs, ensuring seamless validation throughout the implementation phase. Key responsibilities include working closely with design, verification, and physical design teams to enable robust testability solutions for new silicon devices, bare die, and stacked die models. This role demands expertise in JTAG protocols, scan and BIST architectures, ATPG, and EDA tools such as TestMax, Tetramax, Tessent, and PrimeTime, along with experience in gate-level simulation using VCS and other simulators. Ideal candidates have a background in Verilog design, DFT CAD development, test static timing analysis, and post-silicon validation techniques.

Skills

Jtag Scan BIST ATPG TestMax Tetramax Tessent PrimeTime VCS Verilog System Verilog Gate level simulation DFT EDA tools Test Static Timing Analysis CI/CD

What you'll do

Define and implement post-silicon strategies for hardware design.
Develop and integrate innovative DFT IP with RTL designs.
Enable integration of test logic in all phases of implementation flows.
Collaborate on creation of re-usable test and debug strategies for silicon devices.
Craft solutions and debug issues with minimal guidance from mentors.

What we're looking for

Bachelor's or Master's Degree in Electrical or Computer Engineering with at least 10 years of experience.
Extensive post-silicon debug experience from first silicon to production.
Proficiency with JTAG protocols and DFT architectures like Scan and BIST, including memory BIST and boundary scan.
Experience using ATPG and EDA tools such as TestMax, Tetramax, Tessent, and PrimeTime.
Strong background in gate level simulation and debugging with VCS and other simulators.

Sr. ASIC DFT Engineer (Silicon)

SpaceX

Sunnyvale, CA 2 days ago $135,000–$160,000

Siemens_Tessent Perl Python Tcl C++ IEEE_1500 IEEE_1687 Teradyne Advantest Streaming_Scan_Network ATPG SDF_annotated_gate_level_simulations In-System_Test boundary_scan functional_testing board_level_diagnostics

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