ASIC Design Engineer

Cisco

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$165,000–$241,400 / yr
Posted
2 days ago
Closes
Jul 10, 2026

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $191k
This role $203k
$139k most similar roles pay here $252k

This role pays more than 64% of similar roles. Most pay $165,250–$216,250 — the shaded band above. At the midpoint, this role pays about $203k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 174 open roles on FindRole.

Listed pay typically runs $165,000–$241,400 across 174 roles with salary data.

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At a glance

TL;DR · ASIC Design Engineer

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Join Cisco's cutting-edge ASIC design team as a senior RTL designer, contributing to the development of high-performance subsystems for next-generation data center silicon. Your daily tasks will include designing and implementing Verilog/System Verilog code for complex ASICs while collaborating with verification teams to ensure functional coverage and resolving timing and synthesis challenges with physical design teams. You’ll also debug issues across various environments and contribute to post-silicon validation efforts. Ideal candidates have experience in full ASIC tapeouts, high-performance RTL design, and a deep understanding of power optimization techniques. Preferred qualifications include expertise in data center networking architectures, ARM-based SoC protocols, and proficiency in scripting languages like Python or Perl for automation tasks.

Skills

Verilog SystemVerilog Python Perl TCL shell PCIe Ethernet_MAC DDR_LPDDR DMA_engines AXI CHI APB AHB RDMA NVMe-over-TCP ASIC_design_flows static_timing_analysis emulation formal_verification

What you'll do

  • Design and implement high-frequency, high-performance RTL in Verilog/System Verilog.
  • Develop design specifications and participate in technical reviews for ASIC subsystems.
  • Collaborate with verification teams to resolve design issues and achieve functional coverage closure.
  • Address timing, synthesis, and place-and-route challenges with physical design teams.
  • Debug and root-cause issues across simulation, system integration, and silicon bring-up environments.

What we're looking for

  • At least one full ASIC tapeout experience at advanced technology nodes.
  • Expertise in Verilog/System Verilog for high-performance RTL design.
  • Knowledge of timing closure and power optimization techniques.
  • Experience with ASIC design flows including simulation and synthesis.
  • Strong debug and problem-solving skills for complex issues.

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