ASIC Design Verification Engineering Technical Leader

Cisco

Remote

Quick summary

Work type: Remote
Location: San Jose, CA
Salary: $183,800–$263,600 / yr
Posted: 11 days ago
Closes: Jul 17, 2026

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $191k

This role $224k

$139k most similar roles pay here $277k

This role pays more than 83% of similar roles. Most pay $165,400–$216,250 — the shaded band above. At the midpoint, this role pays about $224k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 174 open roles on FindRole.

Listed pay typically runs $165,000–$241,400 across 174 roles with salary data.

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At a glance

TL;DR · ASIC Design Verification Engineering Technical Leader

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Join Cisco’s high-end switching team as a senior ASIC design verification engineer where you will lead the development and maintenance of DV environments for complex chip designs. Your daily tasks include creating simulation models, test plans, and coverage strategies while collaborating with designers and software teams to resolve post-silicon issues. You’ll also mentor junior engineers and contribute to chip architecture discussions. Ideal candidates have extensive experience in ASIC verification using System Verilog and UVM, along with expertise in emulation platforms like Veloce or Palladium. Proficiency in Linux, C/C++, Python/Perl, and networking is essential for this role, which demands a strong background in electrical or computer engineering and hands-on leadership skills.

Skills

SystemVerilog UVM Linux C C++ Python Perl Veloce Palladium Zebu HAPS Networking Dashboard_management CI/CD

What you'll do

Lead and develop block, cluster, and top-level Design Verification (DV) environment infrastructure.
Construct testbenches including scoreboard, agents, sequencers, and monitors for verification.
Develop simulation models, direct tests, random tests, code coverage, and multi-chip/system simulations.
Mentor junior engineers on project tasks and problem-solving techniques in ASIC design verification.
Collaborate with designers and architects to debug issues during post-silicon bring-up and integration.

What we're looking for

Bachelor’s degree in Electrical or Computer engineering with 10+ years of ASIC Design and Verification experience.
Master’s degree in Electrical or Computer engineering with 8+ years of ASIC Design and Verification experience.
Experience leading verification methodology (UVM) for clusters/subsystems or full chip level.
Prior people management experience and expertise in debugging, methodology, and tools.
Proficiency in System Verilog, Linux, C/C++, Python/Perl, and networking.
Experience with emulation platforms like Veloce, Palladium, Zebu, or HAPS.

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