ASIC Engineer - SDC

Cisco

Hybrid Actively hiring
San Jose, CA Posted 18 days ago $165,000–$241,400 / year
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At a glance

AI generated

TL;DR

Join Cisco’s Silicon One team in San Jose as an experienced ASIC engineer responsible for developing full-chip timing constraints and driving Static Timing Analysis (STA) across complex networking SoCs. You will work closely with RTL designers, physical design, and DFT teams to resolve timing issues and ensure constraint correctness throughout the design hierarchy. Key responsibilities include defining clocking architectures, integrating third-party IP constraints, and contributing to timing closure for multiple modes and corners. Ideal candidates have a strong background in Static Timing Analysis using tools like Synopsys PrimeTime or Cadence Tempus, experience with complex networking SoCs, and proficiency in scripting languages such as Python and TCL. This role offers the unique blend of startup culture and large-scale resources within Cisco’s expansive silicon organization.

Skills

Synopsys_PrimeTime Cadence_Tempus TCL Python Perl SDC STA RTL DFT ASIC ARM_CPUSubsystem Third-party_IP_Integration Clocking_Architectures CDC_Analysis SpyGlass_CDC TCM CCD

What you'll do

  • Own and develop full-chip timing constraints (SDC) for complex networking SoCs.
  • Drive Static Timing Analysis (STA) to resolve timing issues with RTL and physical design teams.
  • Define and maintain clocking architectures and constraint models across the design hierarchy.
  • Integrate third-party IP vendor timing constraints into the full-chip SoC environment.
  • Develop block-level SDCs and ensure constraint correctness throughout the design process.
  • Contribute to timing closure and silicon readiness for multiple modes, corners, and conditions.
  • Analyze RTL structures to guide timing-driven micro-architectural improvements.

What we're looking for

  • Bachelor’s degree in Electrical or Computer Engineering with 7+ years of ASIC experience.
  • Expertise in developing full-chip and block-level SDC constraints for complex SoCs.
  • Proficiency in Static Timing Analysis (STA) using Synopsys PrimeTime or Cadence Tempus.
  • Experience integrating third-party IP timing constraints into full-chip environments.
  • Understanding of RTL design, synthesis, and ability to guide timing-driven improvements.
  • Ability to define and maintain clocking architectures for complex SoCs with multiple domains.

Market check

Salary context

This $165,000–$241,400 range sits above 65% of similar postings on FindRole.

Peer median band

$142,580–$221,800

Median floor and ceiling across peers.

Typical midpoint (25–75%)

$152,656–$216,250

Middle half of comparable postings.

Based on 240 comparable postings.

* 240 is the maximum number of comparable postings sampled.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 103 open roles on FindRole.

Listed pay typically runs $165,000–$241,400 across 103 roles with salary data.

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