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SoC Architecture SystemVerilog Verilog VHDL AMBA Synthesis Formal Verification CDC DFT Timing Closure Git JIRA DRAM SERDES UART Design Validation +11 more Show less

ASIC Design IC Design Floor Planning Routing Timing Analysis Physical Verification Signal Integrity Power Integrity SerDes CMOS Clocking Structures +6 more Show less

ASIC Design Physical Design VLSI Place&Route Verilog DRC LVS STA Tcl Perl Python UNIX Linux DSP EDA Tools +10 more Show less

ASIC Design IC Design Floor Planning Routing Timing Analysis Physical Verification SerDes Signal Integrity Power Integrity CMOS Clocking Structures +6 more Show less

IC Package Design Flip-chip BGA ASIC SerDes Signal Integrity Power Integrity HBM DDR5 Cadence APD Allegro Package Designer Cadence SKILL Physical Design Layout RF Microwave ADC DAC +12 more Show less

Place and Route Timing Closure STA Floor-planning Clock Tree Synthesis Physical Verification LVS DRC Equivalence Checks Power Optimization ECO ICC2 Innovus Primetime Caliber LEC SoC Design +12 more Show less

Analog Design CMOS Cadence Virtuoso Cadence Analog Artist Layout Design ATE Bench Testing Post-Silicon Evaluation Buck Converters ADCs DACs OpAmps BCD Technologies Extraction +9 more Show less

IC Package Design Flip-chip BGA ASIC SerDes Signal Integrity Power Integrity Thermal Manufacturability Cadence APD Allegro Package Designer Cadence SKILL Physical Design Layout HBM DDR5 RF Microwave ADC DAC +14 more Show less

VLSI RTL Design Verilog HDL Cache Architecture CPU Coherency NoC SoC Scripting Microarchitecture Timing Closure Design for Test Physical Design Routing Fabric +8 more Show less

RTL Design Verilog HDL Microarchitecture clock-domain crossing Power Management Voltage Management Scripting Tapeout Closure Design-for-Test Physical Design Control Fabric +6 more Show less

Python C++ Tcl Ruby Perl Verilog HDL UNIX Linux Digital Logic Design Static Timing Analysis Data Structures OO Design IC Design Synthesis Verification +10 more Show less

Flip-chip BGA ASIC SerDes Signal Integrity Power Integrity Cadence APD Allegro Package Designer Cadence SKILL Physical Design Layout HBM DDR5 RF Microwave ADC DAC Manufacturability Automation +13 more Show less

ASIC Design VLSI CMOS Physical Design Floorplanning Placement Clock Tree Synthesis Routing Timing Closure DRC LVS IR/EM Checks RTL to GDSII UNIX Linux TCL Python Perl Cadence Innovus Synopsys ICC2 PrimeTime +16 more Show less

Static Timing Analysis (STA) Synopsys PrimeTime Cadence Tempus Tcl Python Perl Ruby Linux VLSI Design ASIC Physical Design MMMC POCV SOCV LVF PBA SPICE Signal Integrity Clock Network Design +13 more Show less

VLSI ASIC Physical Design Static Timing Analysis Synopsys PrimeTime Cadence Tempus TCL Python Ruby BASH SPICE CMOS Clock Networks Signal Integrity Crosstalk POCV SOCV LVF PBA 3DIC +14 more Show less

system Verilog Verilog Python C++ Perl UVM C Shell MySQL PHP Linux Unix Windows Hardware Design Verification Digital Systems Computer Organization Logic Design HDL Oscilloscopes Logic Analyzers +15 more Show less

system Verilog Verilog UVM Python C++ C Perl Shell MySQL PHP Linux Unix Windows Hardware Design Verification Digital Systems Computer Organization Logic Design HDL Oscilloscopes Logic Analyzers Multimeters +16 more Show less

VLSI Physical Design FinFET Verilog RTL Computer Architecture Clock Tree Synthesis Static Timing Analysis Physical Verification Sign Off IR Drop Analysis Parasitic Extraction Floor planning Perl C Tcl SRAM Digital Circuits +12 more Show less

SystemVerilog UVM SVA RTL Gate-level Netlist Python Perl Tcl FPGA Emulation Synopsys Cadence Mentor Git DesignSync Mixed-Signal SDF Co-simulation +13 more Show less

SystemVerilog RTL Design PPA Optimization CDC) analysis RDC Low-Power Design SoC Integration SerDes LPDDR DDR HBM Timing Closure Physical Design +8 more Show less