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Active Keyword: Design Engineer Remove filter Location: Fort Collins Remove filter Clear all

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Design Engineer - Chip Floorplanner

Broadcom

Fort Collins, CO 25 days ago $127,100–$203,400
Actively hiring Verified listing Below market
TCL Linux Python Perl Ruby Cadence VLSI ASIC floorplanning die partitioning hierarchical design PLLs clock networks power delivery timing-critical structures physical verification DRC LVS congestion analysis power analysis PPA optimization
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Design Engineer

Broadcom

Fort Collins, CO 101 days ago $60,200–$96,300
Actively hiring Verified listing Below market
UNIX Linux TCL Python Perl Cadence_Innovus Synopsys_ICC2 PrimeTime VLSI CMOS_logic digital_circuit_fundamentals floorplanning placement routing timing_closure physical_verification DRC LVS block_level_integration EDA_tools
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