Design Engineer - STA

What you'll do

• Develop, validate, and maintain timing constraints for complex SoC designs across multiple modes and corners.
• Perform static timing analysis (STA) using industry-standard tools like Synopsys PrimeTime or Cadence Tempus.
• Define and execute timing signoff methodologies including process corners, derates, and uncertainties.
• Conduct pre- and post-route timing analysis and quality of results (QoR) evaluations.
• Generate and validate timing ECOs to achieve signoff-quality closure across PVT corners.
• Automate timing flows and analysis using Tcl, Python, or Perl scripting languages.
• Analyze and debug timing violations, signal integrity issues, and clock network challenges.
• Support power and performance optimization through informed timing analysis and constraint tuning.

What we're looking for

• Bachelor's degree in Electrical or Computer Engineering with 8+ years of relevant experience.
• Master's degree in Electrical or Computer Engineering with 6+ years of relevant experience.
• Proficiency in performing static timing analysis using Synopsys PrimeTime or Cadence Tempus tools.
• Expertise in developing and validating timing constraints for complex SoC designs across multiple modes and corners.
• Strong proficiency in Tcl scripting and experience with Python, Perl, or Ruby.
• Deep understanding of VLSI design principles, physical design fundamentals, and signal integrity analysis.
• Knowledge of advanced STA techniques including POCV/SOCV/LVF, PBA, and SPICE correlation.
• Ability to collaborate with cross-functional teams and provide technical leadership in methodology improvements.