Design Engineer, STA

Broadcom

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Fort Collins, CO
Salary: $109,700–$175,500 / yr
Employment: Full-time
Posted: 56 days ago
Freshness: Confirmed live yesterday
Closes: Feb 28, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $194k

This role $143k

$96k $240k

below market most similar roles pay here above market

This role pays less than 88% of similar roles. Most pay $162,875–$225,300 — the blue band above. At the midpoint, this role pays about $143k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 280 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 169 roles with salary data.

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At a glance

TL;DR · Design Engineer, STA

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Design Engineer - STA joins the Custom Silicon Design Team within the ASIC Products Division. This role focuses on chip-level timing architecture, analysis, and closure for high-performance SoCs operating at speeds exceeding 1 GHz. You will develop and maintain timing constraints, perform static timing analysis, and execute signoff methodologies for advanced ASICs using 3 nm and smaller process nodes. Key responsibilities include conducting pre- and post-route analysis, generating timing ECOs, and automating flows using Tcl, Python, Perl, or Ruby. You will utilize Synopsys PrimeTime or Cadence Tempus to address signal integrity, crosstalk, and clock network challenges. The work involves solving complex timing environments for AI, cellular, networking, and storage products, ensuring full compliance with timing signoff checklists and methodology across multiple design hierarchies.

Skills

Static Timing Analysis (STA) Synopsys PrimeTime Cadence Tempus Tcl Python Perl Ruby Linux VLSI Design ASIC Physical Design MMMC POCV SOCV LVF PBA SPICE Signal Integrity Clock Network Design

What you'll do

Develop, validate, and maintain timing constraints for complex SoC designs across multiple modes and corners.
Perform static timing analysis using industry-standard tools like Synopsys PrimeTime or Cadence Tempus.
Define and execute timing signoff methodologies including process corners, derates, and uncertainties.
Conduct pre- and post-route timing analysis and quality of results evaluations.
Generate and validate timing ECOs to achieve signoff-quality closure across PVT corners.
Automate timing flows and analysis using Tcl, Python, or Perl scripting.
Analyze and debug timing violations, signal integrity issues, and clock network challenges.
Support power and performance optimization through timing analysis and constraint tuning.

What we're looking for

BS in Electrical or Computer Engineering with 8+ years of relevant experience.
MS in Electrical or Computer Engineering with 6+ years of relevant experience.
Deep understanding of VLSI design principles and ASIC physical design fundamentals.
Proficiency in timing constraint creation, debugging, and validation.
Strong understanding of RC networks, signal integrity, crosstalk delay, and noise analysis.
Strong experience with Tcl scripting and Linux/UNIX environments.
Proficiency in Python, Perl, or Ruby (preferred).
Hands-on experience with Synopsys and/or Cadence STA tools (highly desirable).

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