Design Engineer, STA

Broadcom

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Fort Collins, CO
Salary: $129,400–$207,000 / yr
Employment: Full-time
Posted: 64 days ago
Freshness: Confirmed live yesterday
Closes: Feb 20, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $194k

This role $168k

$118k $238k

below market most similar roles pay here above market

This role pays less than 71% of similar roles. Most pay $162,375–$225,300 — the blue band above. At the midpoint, this role pays about $168k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 280 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 169 roles with salary data.

Most-posted roles

View all roles at Broadcom

At a glance

TL;DR · Design Engineer, STA

Role Posting Log in to save

The Design Engineer - STA joins a team focused on complex VLSI and ASIC physical design challenges. This role involves independent judgment to analyze data, evaluate design constraints, and coordinate with global teams. The engineer will create and debug timing constraints, generate timing reports, and resolve warning or error messages from timing tools. Key responsibilities include performing setup and hold analysis, understanding RC networks, and managing signal integrity, crosstalk delay, and glitch noise analysis. Required technical skills include proficiency in Synopsys PrimeTime, Cadence Tempus, and TCL coding, with preferred experience in Python, Ruby, and BASH. The role addresses critical timing propagation issues, including POCV/SOCV/LVF modeling, MIS, and path-based analysis for SOIC or 3DIC designs, ensuring robust performance across complex semiconductor architectures.

Skills

VLSI ASIC Physical Design Static Timing Analysis Synopsys PrimeTime Cadence Tempus TCL Python Ruby BASH SPICE CMOS Clock Networks Signal Integrity Crosstalk POCV SOCV LVF PBA 3DIC

What you'll do

Perform static timing analysis using Synopsys PrimeTime or Cadence Tempus tools.
Create and debug timing constraints and interpret timing tool error messages.
Generate and analyze timing reports to ensure proper signal propagation.
Analyze RC networks, signal integrity, crosstalk delay, and glitch/noise effects.
Conduct setup and hold analysis along with other critical timing checks.
Develop and execute scripts using TCL, Python, Ruby, or BASH.
Perform SPICE analysis to validate circuit behavior and performance.
Manage and present large datasets to communicate technical results clearly.

What we're looking for

BS degree in Electrical Engineering or Computer Engineering and 12+ years related experience.
MS degree in Electrical Engineering or Computer Engineering and 10+ years related experience.
Strong understanding of VLSI and ASIC physical design.
Basic understanding of PLLs, clock networks, flip flops, latches, memories, and basic CMOS logic gates.
Experience using a static timing analysis tool, preferably Synopsys PrimeTime and/or Cadence Tempus.
Ability to create and debug timing constraints, understand tool messages, and generate timing reports.
Understanding of RC networks, Signal Integrity, Crosstalk Delay, and Glitch/Noise Analysis.
Coding experience in TCL is required; experience with Python, Ruby, or BASH is preferred.

Similar roles

Design Engineer, STA

Broadcom

Fort Collins, CO 56 days ago $109,700–$175,500

Static Timing Analysis (STA) Synopsys PrimeTime Cadence Tempus Tcl Python Perl Ruby Linux VLSI Design ASIC Physical Design MMMC POCV SOCV LVF PBA SPICE Signal Integrity Clock Network Design

8+ yrs exp

Save