Design Engineer - STA

Broadcom

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Fort Collins, CO
Salary
$129,400–$207,000 / yr
Posted
18 days ago
Freshness
Confirmed live yesterday
Closes
Feb 20, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $186k
This role $168k
$118k most similar roles pay here $240k

This role pays less than 70% of similar roles. Most pay $158,862–$214,000 — the shaded band above. At the midpoint, this role pays about $168k versus about $186k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 119 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 105 roles with salary data.

Most-posted roles

View all roles at Broadcom

At a glance

TL;DR · Design Engineer - STA

Role Posting Log in to save

As a Design Engineer - STA, you will join the team to address complex development and support issues involving VLSI and ASIC physical design. You will be responsible for creating and debugging timing constraints, generating and interpreting timing reports, and analyzing signal integrity, crosstalk delay, and noise. The role requires managing large amounts of data while collaborating with global teams to solve intricate design problems. You will utilize tools such as Synopsys PrimeTime or Cadence Tempus, along with TCL, Python, Ruby, and BASH for scripting. Technical expertise must include RC networks, PLLs, clock networks, and advanced concepts like POCV/SOCV modeling and Liberty timing models. This position focuses on the critical physical design challenges of semiconductor chips, ensuring proper timing propagation and reliability across complex integrated circuit architectures.

Skills

STA VLSI ASIC Physical Design Synopsys PrimeTime Cadence Tempus TCL Python Ruby BASH SPICE CMOS Signal Integrity Timing Constraints RC Networks 3DIC SOIC

What you'll do

  • Perform static timing analysis (STA) using tools like Synopsys PrimeTime or Cadence Tempus.
  • Create and debug complex timing constraints for VLSI and ASIC physical designs.
  • Analyze and resolve warning and error messages from timing tools to ensure design integrity.
  • Evaluate signal integrity, crosstalk delay, and glitch/noise impacts on timing propagation.
  • Develop and execute scripts using TCL, Python, or Bash to automate tasks and manage data.
  • Perform advanced STA modeling including POCV/SOCV, LVF, and various liberty timing models.
  • Conduct SPICE analysis and evaluate RC networks for signal timing accuracy.
  • Resolve complex design issues by applying engineering judgment to technical constraints and implementation techniques.

What we're looking for

  • BS degree in Electrical Engineering or Computer Engineering and 12+ years related experience, or an MS degree and 10+ years related experience.
  • Strong understanding of VLSI and ASIC physical design.
  • Basic understanding of PLLs, clock networks, flip flops, latches, memories, and basic CMOS logic gates.
  • Experience using static timing analysis tools like Synopsys PrimeTime or Cadence Tempus (preferred).
  • Ability to create and debug timing constraints and interpret tool warning/error messages.
  • Understanding of RC networks, Signal Integrity, Crosstalk Delay, Glitch/Noise Analysis, and various timing checks.
  • Required experience in TCL coding; experience with Python, Ruby, or BASH is preferred.
  • Advanced STA concepts such as POCV/SOCV/LVF modeling, MIS, CCS/ECSM/NLDM, PBA, and LOCV/SOCV (preferred).

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