Design Implementation Engineer

Broadcom

Confirmed live today High trust

Quick summary

Work type: On-site
Location: San Jose, CAAllentown, PAFort Collins, COBroomfield, CO
Salary: $121,900–$195,000 / yr
Employment: Full-time
Posted: 8 days ago
Freshness: Confirmed live today
Closes: Apr 17, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $189k

This role $158k

$109k $238k

below market most similar roles pay here above market

This role pays less than 74% of similar roles. Most pay $158,450–$219,812 — the blue band above. At the midpoint, this role pays about $158k versus about $189k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 280 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 169 roles with salary data.

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At a glance

TL;DR · Design Implementation Engineer

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The Design Implementation Engineer will join the team to execute design implementation activities for ASIC and SoC designs. The role involves performing floor-planning, partitioning, placement, clock tree synthesis, routing, and physical verification including LVS and DRC. The engineer will drive tools and methodologies to achieve specific PPA metrics while performing equivalence checks, static timing analysis, and power optimization. Key responsibilities include implementing timing and functional ECOs to meet rigorous criteria for right-first time silicon. Required technical skills include proficiency with Primetime, ICC2, Innovus, Caliber, and LEC. The candidate must have experience with 7nm and lower technologies, focusing on timing closure and constraints development. This position solves complex physical design problems to ensure successful chip tapeouts in a dynamic global environment.

Skills

Place and Route Timing Closure STA Floor-planning Clock Tree Synthesis Physical Verification LVS DRC Equivalence Checks Power Optimization ECO ICC2 Innovus Primetime Caliber LEC SoC Design

What you'll do

Execute design implementation activities including floor-planning, partitioning, placement, and clock tree synthesis.
Perform route, timing analysis, and timing closure to achieve desired PPA metrics.
Conduct physical verification tasks including LVS and DRC checks.
Perform static timing analysis (STA) and equivalence checks.
Implement timing and functional ECOs to resolve design issues.
Execute power optimization techniques during the design flow.
Apply design methodologies to meet rigorous criteria for right-first-time silicon.

What we're looking for

BS in Electrical Engineering/Computer Engineering or related field and 8+ years of related experience.
MS in Electrical Engineering/Computer Engineering or related field and 6+ years of related experience.
Hands-on experience with timing analysis and place and route tools for ASIC/SoC Design.
Proficiency in floor-planning, partitioning, placement, clock tree synthesis, routing, and physical verification.
Experience with timing analysis, timing closure, constraints development, and power optimization.
Experience with formal verification, equivalence checks, and ECO implementation.
Experience with tools such as Primetime, ICC2, Innovus, Caliber, and LEC (preferred).
Tapeout experience for at least 1-2 ASICs in 7nm or lower technologies (preferred).

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