Digital Design RTL Engineer

Broadcom

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Quick summary

Work type
On-site
Location
Fort Collins, COSan Jose, CA
Employment
Full-time
Posted
72 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

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Similar $198k
$140k most similar roles pay here $243k

This listing doesn't post a salary. Most similar roles pay $167,075–$229,100.

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About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 223 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 160 roles with salary data.

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At a glance

TL;DR · Digital Design RTL Engineer

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As a Digital Design RTL Engineer, you will join the team to develop high-quality SystemVerilog RTL for advanced process nodes at 5nm and below. You will operate with a high degree of autonomy, taking designs from initial specification through timing closure and physical design hand-off while collaborating cross-functionally with Architecture, Verification, and Physical Design teams to mitigate risks and meet project milestones. Your daily work involves performing PPA optimization, clock domain crossing analysis, and implementing low-power design techniques. The role requires expertise in SystemVerilog and experience with SoC integration, high-speed SerDes, LPDDR/DDR, and HBM protocols. You will solve complex technical challenges related to advanced semiconductor manufacturing and integrated circuit design, ensuring that the hardware meets rigorous performance and power specifications within the specified advanced technology nodes.

Skills

SystemVerilog RTL Design PPA Optimization CDC) analysis RDC Low-Power Design SoC Integration SerDes LPDDR DDR HBM Timing Closure Physical Design Advanced Process Nodes

What you'll do

  • Deliver high-quality SystemVerilog RTL for advanced process nodes (5nm and below).
  • Manage the full design lifecycle from initial specification through timing closure and physical design hand-off.
  • Perform PPA optimization to improve power, performance, and area metrics.
  • Conduct clock domain crossing (CDC) and reset domain crossing (RDC) analysis.
  • Implement low-power design techniques within the RTL.
  • Mitigate project risks by coordinating with Architecture, Verification, and Physical Design teams.

What we're looking for

  • A Bachelor of Science in Electrical Engineering is required.
  • A Master's degree or PhD is preferred.
  • High proficiency in SystemVerilog is required.
  • Experience delivering high-quality SystemVerilog RTL in advanced process nodes (5nm and below) is required.
  • Deep understanding of PPA optimization, clock domain crossing (CDC), and Reset Domain crossing (RDC) is required.
  • Knowledge of low-power design techniques is required.
  • 5+ years of industry experience with a focus on SoC integration, high-speed SerDes, LPDDR/DDR, and/or HBM protocols is preferred.

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