Design Engineer

Broadcom

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Fort Collins, CO
Employment
Full-time
Posted
36 days ago
Freshness
Confirmed live yesterday
Closes
Feb 20, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

How this pay compares to similar roles

Similar $195k
$135k most similar roles pay here $239k

This listing doesn't post a salary. Most similar roles pay $160,590–$229,100.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 228 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 158 roles with salary data.

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At a glance

TL;DR · Design Engineer

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As a Design Engineer within the Custom Silicon Design Team in the ASIC Products Division, you will contribute to the physical implementation of large-scale, high-performance ASICs with multi-hundred-million gate complexity. You will perform critical tasks including floorplanning, placement, clock tree synthesis, routing, timing closure, and physical verification such as DRC and LVS. The role involves managing the full design cycle from RTL to GDSII for products in the AI, Cellular, Networking, Computing, and Storage spaces using 3 nm and smaller process nodes. You will utilize both commercial and in-house EDA tools like Cadence Innovus, Synopsys ICC2, or PrimeTime. Required skills include a solid understanding of VLSI design and CMOS logic, proficiency in UNIX/Linux environments, and working knowledge of TCL, with Python or Perl preferred for automation and flow improvements.

Skills

ASIC VLSI CMOS Floorplanning Placement Clock Tree Synthesis Routing Timing Closure DRC LVS IR/EM RTL GDSII UNIX Linux TCL Python Perl Cadence Innovus Synopsys ICC2 PrimeTime

What you'll do

  • Execute physical design implementation for large-scale ASICs with multi-hundred-million gate complexity.
  • Perform floorplanning, placement, clock tree synthesis, routing, and timing closure.
  • Conduct physical verification including DRC and LVS checks.
  • Perform power planning, IR/EM checks, and post-route optimization.
  • Develop and improve design flows, automation, and deep sub-micron methodologies.
  • Utilize commercial and in-house EDA tools for design, implementation, and verification.
  • Participate in the full ASIC design cycle from RTL to GDSII and silicon bring-up.
  • Support technical discussions and design reviews with customers and internal stakeholders.

What we're looking for

  • Bachelor's degree in Electrical or Electronics Engineering.
  • Master's degree in Electrical or Electronics Engineering.
  • Solid understanding of VLSI design, CMOS logic, and digital circuit fundamentals.
  • Familiarity with ASIC physical design concepts such as placement, routing, and timing.
  • Proficiency in UNIX/Linux environments.
  • Working knowledge of TCL (preferred).
  • Familiarity with Python or Perl (preferred).
  • Exposure to EDA tools such as Cadence Innovus, Synopsys ICC2, or PrimeTime (preferred).

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