Package Design Engineer

Broadcom

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Jose, CAAustin, TXFort Collins, CO
Salary
$82,500–$132,000 / yr
Posted
3 days ago
Freshness
Confirmed live yesterday
Closes
Mar 7, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $173k
This role $107k
$67k most similar roles pay here $225k

This role pays less than 97% of similar roles. Most pay $146,500–$199,199 — the shaded band above. At the midpoint, this role pays about $107k versus about $173k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 119 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 105 roles with salary data.

Most-posted roles

View all roles at Broadcom

At a glance

TL;DR · Package Design Engineer

As a Package Design Engineer, you will join a worldwide R&D team to develop high-performance package designs for ASICs used in artificial intelligence, networking, high-performance computing, and 5G base stations. You will take overall design responsibility for complex flip-chip-BGA packages, focusing on critical structures for SerDes at 224G and higher, 5G RF/Microwave ADC/DAC, HBM, and DDR5. Your daily work involves managing multiple projects simultaneously while addressing signal integrity, power integrity, manufacturability, reliability, and thermal requirements. You will perform physical design layout and contribute to team efficiency through process development and automation. The role requires expertise in electrical engineering fundamentals and experience with Cadence APD or similar tools. Preferred candidates possess skills in Cadence SKILL for Allegro or other design-automation coding to solve complex high-speed and very-high-power delivery challenges.

What you'll do

  • Perform overall design for ASIC packages including signal integrity, power integrity, manufacturability, reliability, and thermal management.
  • Design critical package structures for high-speed components like SerDes, ADC/DAC, DDR, and HBM.
  • Execute physical layout designs as a foundational component of the engineering role.
  • Manage project schedules, priorities, and tracking across multiple simultaneous projects.
  • Act as the primary point of contact for project management and customer interface.
  • Develop process improvements, automation tools, and documentation to increase team efficiency.
  • Coordinate with internal teams and external vendors across multiple time zones.

What we're looking for

  • BSEE or similar field degree, MSEE, or PhD.
  • 2+ years of experience in flip-chip-BGA package design including high-speed SerDes.
  • Knowledge of electrical engineering fundamentals.
  • Working knowledge of package-level signal integrity and power integrity (preferred).
  • Experience with Cadence APD or an equivalent layout tool.
  • Cadence SKILL for Allegro or similar design-automation coding experience (preferred).
  • Ability to manage multiple projects simultaneously while collaborating with a worldwide team.
  • Strong self-management and organization skills.

More like this

Similar roles

Package Design Engineer

Broadcom

San Jose, CA +2 42 days ago $121,900$195,000
Flip-chip BGA SerDes Signal Integrity Power Integrity Cadence APD Allegro Package Designer Cadence SKILL HBM DDR5 RF/Microwave Layout Automation Process Development
8+ yrs exp

Package Design Engineer

Broadcom

San Jose, CA +2 102 days ago $141,300$226,000
Flip-chip BGA SerDes Signal Integrity Power Integrity Cadence APD Allegro Package Designer Cadence SKILL ASIC HBM DDR5 RF Microwave Layout Automation Manufacturability Reliability
10+ yrs exp

Senior IC Package Design Engineer

SpaceX

Austin, TX 113 days ago
IC Package Design ASIC RFIC BGA SIP Power Integrity EM Simulation Cadence APD+ SIWave HFSS ADS Co-packaged Optics Substrate Design Tapeout Mixed Signal
5+ yrs exp

Package Design Engineer, Staff

Qualcomm

San Diego, CA 50 days ago $154,000$231,000
Cadence APD Siemens Xpedition Cadence Allegro SiP SI/PI DRC DFM ERC XtractIM PowerSI HFSS Q3D Calibre DDR PCIe UCIe S-parameters RLGC High-speed IO
5+ yrs exp

Packaging Design Engineer

Amd

San Jose, CA +1 38 days ago $200,000$300,000
Cadence SKILL Ansys AutoCAD PCB Layout Package Design Power Integrity SerDes DoE DFM DFR Modeling and Simulation
Hybrid

IC Package Design Engineer

Cisco

Remote (San Jose, CA) 53 days ago $152,500$219,200
ASIC Package Design PCB Design SI/PI high‑speed signaling Power Delivery EDA Tools Python Perl TCL multi‑die systems Interposers Floorplanning stack‑up definition Pinout Optimization
5+ yrs exp Remote