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Physical Design Static Timing Analysis Logic Synthesis Floorplanning Clock-tree Synthesis Routing ECO RTL Python Tcl Perl Make AI Deep Learning LLMs EDA Tools +11 more Show less

Physical Design GPU SoC Synthesis Floorplanning Placement Routing Clock Tree Synthesis Timing Closure STA Signoff DRC LVS Python Tcl Shell Perl Synopsys Cadence ICC2 Fusion Compiler Innovus PrimeTime Tempus StarRC +20 more Show less

SystemVerilog UVM ASIC Verification VCS Verdi Python C/C++ Perl UPF DFT Functional Coverage Assertion-based Verification Machine Learning SoC GDS Automated Verification Flows +11 more Show less

RTL Verilog Python ASIC DFT Logic Synthesis PPA Silicon Debug Timing Closure Power Optimization Cross-talk OCV Scripting +8 more Show less

SoC RTL Verilog SystemVerilog PCIe DDR LPDDR HBM UCIe Ethernet Python Perl UVM OVM CDC RDC Linting Synthesis Timing Analysis DFT +15 more Show less

ASIC Physical Design Logic Synthesis Static Timing Analysis (STA) Equivalence Checking DFT Python TCL Perl Make EDA Tools Netlist Quality Check Timing Closure ECO Generation Hardware Architecture +9 more Show less

ASIC Design RTL to GDS Flow Virtuoso System Simulation Synthesis Place and Route Scripting Verification Validation SoC IC Package +6 more Show less

SystemVerilog RTL Design Python Perl Shell Scripting Git Static Timing Analysis Logic Synthesis AI/ML Microarchitecture Instruction Set Architecture Digital Design +7 more Show less

Physical Design ASIC Floorplanning Synthesis Placement Clock Tree Synthesis CTS Routing Static Timing Analysis STA Physical Verification Formal Equivalency Power Optimization IR-drop Electromigration EDA Tools +11 more Show less

Python C++ VLSI EDA AI LLMs Signal Integrity Power Delivery Parasitic Extraction IC Physical Design Data Structures Algorithms Object-Oriented Design +8 more Show less

Digital Signal Processing MATLAB C/C++ Serdes RTL Firmware Communication Theory PAM FEC CDR PCIe IEEE 802.3 OIF Signal Processing Algorithms +9 more Show less

SystemVerilog C++ Python GPU Architecture RTL Constrained-Random Testing Functional Coverage Computer Architecture Graphics Pipelines 3D Graphics Verification Testbenches Semiconductor Design +7 more Show less

Verilog HDL RTL SoC ARM PCIe CXL UCIe Ethernet Python Perl CDC RDC Linting Synthesis Timing Analysis DFT Floor Planning Power Management +13 more Show less

PCB Design Cadence Allegro Constraint Manager High-Speed PCB Layout Signal Integrity EMI HDI PCIe SKILL Perl C++ DFM CAM Tools PCB Manufacturing Assembly Scripting Automation +12 more Show less

Digital Signal Processing MATLAB C/C++ Serdes RTL Firmware Communication Theory PAM FEC CDR IEEE 802.3 OIF PCIe Signal Processing Algorithms +9 more Show less

ASIC UVM SystemVerilog Verilog Python Perl VCS Verdi Xcelium Automation RTL Pre-silicon Verification Scripting Infrastructure Simulation Debug Metrics +12 more Show less

Physical Design Floorplanning Placement Routing Clock Tree Synthesis Timing Closure STA Power-grid Design DRC LVS Python Tcl Shell Perl FusionCompiler Innovus PrimeTime Tempus StarRC RedHawk +15 more Show less

ASIC Physical Design Floor Planning Synthesis Verilog TCL Perl Python Shell GPU Architecture Timing Constraints Netlist +7 more Show less

C++ VLSI Physical Design EDA Tools Machine Learning Graph Neural Networks Python Tcl Perl multithreading Distributed Computing ICC2 Innovus PrimeTime Tempus StarRC +10 more Show less

C++ Golang Unix Linux Verilog VLSI Compiler Build Systems Database Dynamic Code Analysis Domain-Specific Languages (DSLs) Computer Architecture RTL Design +8 more Show less