Senior Design Engineer

Arm Holdings

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Austin, TX
Salary
$161,500–$218,500 / yr
Posted
14 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $182k
This role $190k
$126k most similar roles pay here $228k

This role pays more than 66% of similar roles. Most pay $151,375–$213,531 — the shaded band above. At the midpoint, this role pays about $190k versus about $182k for comparable roles.

Based on 240 similar postings.

Employer

About Arm Holdings

Arm Holdings plc is a leading British semiconductor and software design firm, established in 1990 and recognized for developing energy-efficient processor architectures that power nearly all smartphones and a vast range of IoT and computing devices.

Arm Holdings currently has 105 open roles on FindRole.

Listed pay typically runs $209,100–$282,900 across 105 roles with salary data.

Most-posted roles

View all roles at Arm Holdings

At a glance

TL;DR · Senior Design Engineer

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As a Senior Design Engineer, you will join an innovative team focused on integrating PCIe, DDR, and other IP components into complex SoCs. Your daily responsibilities involve writing micro-architecture specifications, developing RTL, fixing bugs, and running design checks such as CDC, RDC, X-Propagation, and Linting. You will collaborate with verification teams to debug issues, partner with performance analysis teams to improve system metrics, and work with backend teams on floor planning and timing closure. The role requires expertise in Verilog HDL, Python, or Perl scripting, along with experience in high-speed protocols like HBM, UCIe, and Ethernet. You will also contribute to design methodologies and mentor team members. This position addresses the technical challenges of designing complex compute subsystems and integrating various hardware components into cohesive system architectures for advanced computing platforms.

Skills

SoC RTL Verilog SystemVerilog PCIe DDR LPDDR HBM UCIe Ethernet Python Perl UVM OVM CDC RDC Linting Synthesis Timing Analysis DFT

What you'll do

  • Integrate PCIe, DDR, and other IP components into SoC designs.
  • Write micro-architecture specifications and develop corresponding RTL code.
  • Fix design bugs and run various design checks including CDC, RDC, and Linting.
  • Collaborate with verification teams to review test plans and debug build issues.
  • Partner with performance analysis teams to evaluate and improve system performance.
  • Assist the backend team with floor planning, writing constraints, and achieving timing closure.
  • Develop and enhance internal design methodologies for the engineering team.
  • Guide and support other team members to ensure successful project completion.

What we're looking for

  • Bachelor's or Master's degree in Computer Science, Electrical/Computer Engineering, or a related field.
  • 7+ years of experience working in the design of complex compute subsystems or SoCs.
  • Strong knowledge of digital hardware design and Verilog HDL.
  • Experience developing and integrating subsystems for PCIe, DDR/LPDDR, HBM, UCIe, and Ethernet.
  • Experience creating design specifications and developing RTL for SoC projects and compute platforms.
  • Experience in static design checks including CDC, RDC, X-Propagation, and Linting.
  • Experience with Perl, Python, or other scripting languages.
  • Experience with ARM-based designs/architectures, SystemVerilog, UVM/OVM, leading teams, synthesis, power management, or DFT (preferred).

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