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UVM System Verilog Python CHI AMBA PCIe CXL Fabric Interconnects Generative AI Simulation +5 more Show less

PCIe UVM System Verilog Python CHI AXI Simulation Generative AI Coverage Signoff +4 more Show less

FPGA VHDL System Verilog UVM OSVVM Quartus Modelsim Questa Sim Python MATLAB Simulink JIRA GIT DSP RTL ASIC LabVIEW AXI Avalon NIOS +15 more Show less

UVM OVM SystemVerilog Assertions (SVA) Verilog VHDL Python TCL Perl Mixed-Signal Verification Logic Synthesis Static Timing Analysis Formal Verification Place and Route EDA Tools CMOS Bipolar Scripting +12 more Show less

Mechanical Engineering MATLAB ANSYS Monte Carlo Methods Design Controls Risk Management Reliability Engineering New Product Development (NPD) Statistical Analysis Modeling Simulation Engineering Analysis Data Analysis +8 more Show less

SolidWorks NX Creo Teamcenter ASME Y14.5 GD&T FEA CAD PLM PDM DFM DFA 3/5-axis CNC Machining Injection Molding Thermal Management RF/EMI Shielding SOPs +12 more Show less

FPGA System on Chip High Density Interconnect (HDI) PCIe Gen3 10GBASE-KR Fiber Optics CAN MIL-STD-1553 ARINC 429 ARINC 664 TSN OpenVPX PIC-SIG DO-254 Mentor Graphics Expedition Hyperlinx PI/SI OrCAD PSPICE LT Spice Mathcad +14 more Show less

Verilog SystemVerilog C++ Python Perl Tcl SoC Design ASIC Design RTL Data Structures Algorithms Synopsys Fusion Compiler AI Coding Tools Claude Code Cursor +10 more Show less

DFT SoC Architecture RTL Design Verilog UVM Post-Silicon Validation ATE Python Perl Tcl STA Power Optimization Fuse Controller Verification Synthesis +10 more Show less

Static Timing Analysis STA Synthesis ECO RTL Floor-planning DFT Python Tcl Make Synopsys PrimeTime Cadence Tempus Physical Design +8 more Show less

PCB Design Oscilloscopes Multimeters Logic Analyzers Linux Windows GPU Tegra System Design +4 more Show less

React TypeScript Figma Design Systems Style Dictionary Storybook CI/CD CSS Custom Properties pnpm Turborepo Changesets SemVer React Aria DTCG Design Tokens Monorepos Visual Regression Testing +11 more Show less

React TypeScript Figma Design Systems Style Dictionary Storybook CI/CD Accessibility ARIA CSS Custom Properties pnpm Turborepo Changesets SemVer Radix React Aria DTCG Monorepos Linting +14 more Show less

Datacenter Design Construction Engineering Architecture Site Due Diligence PMP EPC +1 more Show less

FPGA RTL VHDL Verilog SystemVerilog SoC Python Tcl Linux Git CI/CD Xilinx Ethernet PCIe JESD204 SPI I2C UART CAN MIL-STD-1553 +15 more Show less

RTL Verilog Python ASIC DFT Logic Synthesis PPA Silicon Debug Timing Closure Power Optimization Cross-talk OCV Scripting +8 more Show less

ASIC Design RTL Design SoC Integration Logic Synthesis Timing Analysis Python Perl C++ UCIe Digital Design Verification Methodology Memory Controllers DMA Boot Controllers Fuse Controllers +10 more Show less

SOC Integration RTL Design Python Perl EDA Tools Synthesis Padring Physical Design ASIC Design Design Automation Scripting DFT CAD +8 more Show less

C C++ SystemVerilog Python Perl Ruby FPGA HAPS Xilinx JTAG Logic Analyzers Oscilloscopes UART AMBA AXI AHB APB SPI I2C I3C USB Assembly Linker Scripts Makefile +19 more Show less

Digital Signal Processing MATLAB C/C++ Serdes RTL Firmware Communication Theory PAM FEC CDR PCIe IEEE 802.3 OIF Signal Processing Algorithms +9 more Show less