Senior Staff Physical Design Feasibility Engineer

Samsung Electronics

Remote

Quick summary

Work type: Remote
Location: Remote
Salary: $180,200–$270,400 / yr
Posted: 52 days ago
Closes: Jul 31, 2026

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $182k

This role $225k

$129k most similar roles pay here $286k

This role pays more than 80% of similar roles. Most pay $150,000–$213,375 — the shaded band above. At the midpoint, this role pays about $225k versus about $182k for comparable roles.

Based on 238 similar postings.

Employer

About Samsung Electronics

Samsung Electronics is a South Korean multinational corporation and a global leader in technology, specializing in consumer electronics, semiconductors, and home appliances.

Samsung Electronics currently has 39 open roles on FindRole.

Listed pay typically runs $175,000–$225,000 across 37 roles with salary data.

Most-posted roles

View all roles at Samsung Electronics

At a glance

TL;DR · Senior Staff Physical Design Feasibility Engineer

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As a Senior Staff Physical Design Feasibility Engineer at SARC/ACL, you will lead the optimization of complex ASIC and interposer designs from floor planning to tape-out, ensuring they meet critical PPA goals. Your responsibilities include collaborating with architects and RTL designers to drive architectural definition and improve new features or changes, as well as managing synthesis, floor planning, place & route in chip-level environments. You will also automate design flows using Perl, TCL, Shell scripts, and contribute to the development of our market-leading GPU technology, such as Samsung Galaxy smartphones' Xclipse GPU with ray tracing capabilities. This role requires a solid understanding of SOC/ASIC design flow, block-level floor-planning expertise, and proficiency in scripting languages like TCL and Python, alongside strong communication skills for a collaborative team environment.

Skills

Perl TCL Shell Python Verilog GPU architecture SOC/ASIC design flow P&R tools Floor-planning PPA optimization Logical equivalence checking Timing constraints Scripting Programming

What you'll do

Lead the technical definition of architectural features to meet PPA goals.
Evaluate RTL changes for impact on performance, power, and area efficiency.
Execute synthesis, floor planning, place & route in complex chip designs.
Automate design flows using scripting languages like Perl, TCL, and Shell.
Optimize GPU design modifications to ensure timing, power, and reliability.

What we're looking for

10+ years of experience in SOC/ASIC design with a relevant degree.
Proven ability to deliver high-quality designs meeting PPA goals and requirements.
Solid understanding of SOC/ASIC design flow using industry-standard tools.
Experience in block-level floor-planning and PPA optimization techniques.
Proficient scripting skills in TCL, Perl, Shell, and Python for automation.
Strong knowledge of GPU architecture and data flow principles.
Excellent communication and collaboration skills in a team environment.

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