Senior Staff Physical Design Feasibility Engineer

What you'll do

• Drive PPA performance for complex ASIC and interposer designs from floor planning through tape-out.
• Optimize and validate GPU design modifications to meet timing, power, area, and reliability targets.
• Collaborate with architects to define architecture and deliver micro-architectural level documentation.
• Partner with RTL designers to evaluate and improve new architectural features or RTL changes.
• Execute synthesis, floor planning, and place & route in chip-level and hierarchical environments.
• Deliver RTL/netlist to GDS flow while ensuring proper functionality and PPA goals.
• Develop scripts in Perl, TCL, and Shell to automate design flows and increase efficiency.

What we're looking for

• Must have a Bachelor’s degree with 10+ years of experience, or a Master’s with 8+ years, or a PhD with 6+ years.
• Proven track record of delivering high-quality designs that meet PPA goals and functionality requirements.
• Solid understanding of SoC/ASIC design flow using the latest industry P&R tools.
• Experience in block-level floor-planning and PPA optimization.
• Knowledge of logical equivalence checking, timing constraints, and Verilog.
• Basic understanding of GPU architecture and data flow.
• Proficiency in scripting and programming using TCL, Perl, Shell, and/or Python.
• Must be authorized to access information subject to U.S. export control laws.